Abstract: A method of logic simulation for simulating operation of a logic circuit by using basic signal values corresponding to states of output signals of elements of the logic circuit to be simulated and expanded signal values including the basic signal values. The logic circuit to be simulated is divided into a portion to be simulated by using the basic signal values and the expanded signal values and a portion to be simulated by using the basic signal values without using the expanded signal values. The elements for which definition of calculation method for output signal values for the input signal values including the expanded signal values is not easy are included in the latter portion, and other elements are included in the former portion.

Abstract: A method and apparatus for providing data for adjusting an electronic computer having a main storage unit, in a system including a service processor connected to the electronic computer to maintain the same, and an external storage unit for storing data of internal registers of the electronic computer, which are read out by the service processor. An adjusting program is executed by the electronic computer until a logical failure is detected in the electronic computer to be adjusted. Once the logical failure is detected, execution is stopped at an instruction an arbitrary number of instruction before the instruction on which the failure was detected. Thereafter, the electronic computer is caused to re-execute the adjusting program. Data of internal registers and the main storage unit of the electronic computer is stored in the eternal storage unit through the service processor when the electronic computer stops execution of the adjusting program.

Abstract: A vector processor has a discriminator for determining in one machine cycle of an operation unit whether a bit pattern of elements of vector data meets a predetermined condition or not. An output of a register having a predetermined value loaded only into bits to be extracted from the vector data and each of the elements of the vector data are ANDed or ORed so that the bit pattern is determined. The operation and determination are sequentially carried out in one machine cycle.

Abstract: A logic circuit simulation method for simulating a logic circuit including a plurality of logic blocks, in which after having simulated the whole simulation object logic circuit, signal variation information of an arbitrary logic block is taken out from the simulation result, the information thus taken out is given to the logic blocks, and a renewed simulation is executed for every logic block.

Abstract: A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.

Abstract: In a display terminal equipment, a display device and a plurality of input devices are connected to a controller. Each input device is operated by an operator for inputting information. The controller controls the information entered from a different input device to be displayed on a different display area of the display device. It becomes possible for a plurality of operators to share a single display device and a single display terminal equipment while handling his or her own input device at the same time.

Abstract: In response to the execution of a single loading instruction, the front half and the rear half of a designated vector may be stored in respective vector registers in a single processor operation. For this purpose, a data distribution circuit is interposed between a group of vector registers and a vector data storage for feeding the vector data read out from the storage to a first vector processor designated by an instruction without shifting and for shifting the respective components of the read-out vector data and feeding the shifted components to a second vector register designated by the instruction.

Abstract: In a vector processor for performing an operation on first and second vectors for each vector element, an operation code is set for each vector element of at least one of the first and second vectors to designate the type of an operation to be executed on the vector element, and the operation is carried out on the first and second vectors for each vector element based on the operation code.