Abstract: A dental prosthesis of a dental prosthesis system includes an incurved contact surface that contacts a gingiva. In a first reference cross-sections including first reference lines, a distance between a first point and the dental prosthesis' outer edge on a lingual side satisfies in an incisal portion, where the first point is an intersection of the contact surface and a line connecting a center of a prosthetic tooth and a position that is offset to the lingual side by 3 mm from the prosthetic tooth's base end point, and in a occlusal portion, a distance between a second point and the dental prosthesis' outer edge on the lingual side satisfies, where second point is an intersection of the contact surface and a line connecting a center of a prosthetic tooth and a position that is offset to the lingual side by a/2 from a prosthetic tooth's base end point.

Abstract: When a prescribed value of inner potential is provided from AC voltage received by an input terminal (1), first input means (30) and second input means (20) control gate voltages of first and second transistors (8) and (7), respectively, so that the inner potential may not be influenced by threshold voltage of these transistors.

Abstract: A memory cell formed of two serially connected MOS transistors one of which has a floating gate is connected to a series combination of a Y address MOS transistor, a readout selection MOS transistor and an MOS transistor disposed in an output buffer circuit across two DC sources. A writing selection MOS transistor is connected across the series combination of the last-mentioned two transistors. The Y address MOS transistor, the readout selection MOS transistor, the output buffer MOS transistor and the writing selection MOS transistor are all operated in the triode region with V.sub.G -V.sub.TH >V.sub.D and at least one of these MOS transistors has a channel conductivity type different from the channel conductivity type of the memory cell MOS transistors.

Abstract: In the disclosed FAMOS semiconductor non-volatile memory a source and a drain region of the p.sup.+ type are disposed in an n semiconductor layer to form a gate region between them. The main face of the semiconductor layer is coated with a silicon dioxide film in which a polycrystalline silicon gate is buried to bridge the source and drain regions. An n.sup.+ type high doped semiconductor region is disposed in the semiconductor layer only under the silicon gate to form a pn junction with the drain region. Thus the pn junction is normal to the main face of the semiconductor layer.