Patents by Inventor Yoshiharu Ono
Yoshiharu Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230076961Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a reformed layer former configured to partially reform a first substrate to form a reformed layer between first and second portions in the first substrate, a peeling layer former configured to form a peeling layer between the second portion and a second substrate provided on the first substrate, and a remover configured to remove the second portion from the second substrate while causing the first portion to remain on the second substrate. The remover includes a heater to heat the first or second portion, to peel the second portion from the second substrate at the peeling layer and divide the first and second portions from each other, and a mover to move the second substrate relative to the second portion, to remove the second portion from the second substrate while causing the first portion to remain on the second substrate.Type: ApplicationFiled: February 16, 2022Publication date: March 9, 2023Applicant: Kioxia CorporationInventors: Aoi SUZUKI, Yoshiharu ONO, Ai MORI
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Patent number: 11282723Abstract: According to one embodiment, a liquid delivery member is provided which is to be arranged at a predetermined distance from a processing object, and which is configured to deliver a liquid from a slit while the liquid delivery member and the processing object are caused to make relative displacement therebetween in a first direction. The liquid delivery member includes a delivery amount adjustment part provided on a face that forms the slit, extending in a second direction orthogonal to the first direction, and configured to adjust a delivery amount of the liquid.Type: GrantFiled: September 4, 2019Date of Patent: March 22, 2022Assignee: KIOXIA CORPORATIONInventors: Hironobu Tamura, Ikuo Yoneda, Yoshiharu Ono
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Patent number: 11164843Abstract: According to one embodiment, in a substrate bonding apparatus a first chucking stage includes a first stage base, a plurality of first cylindrical members, and a plurality of first drive mechanisms. The first stage base includes a first main face facing a second chucking stage. The plurality of first cylindrical members are disposed on the first main face. The plurality of first cylindrical members are arrayed in planar directions. The plurality of first cylindrical members protrudes from the first main face in a direction toward the second chucking stage to chuck the first substrate. The plurality of first drive mechanisms are configured to drive the plurality of first cylindrical members independently of each other. The substrate bonding apparatus further comprises a first pressure control mechanism configured to control pressure states of spaces in the plurality of first cylindrical members independently of each other.Type: GrantFiled: March 12, 2020Date of Patent: November 2, 2021Assignee: Kioxia CorporationInventors: Hironobu Tamura, Yoshiharu Ono
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Publication number: 20210082863Abstract: According to one embodiment, in a substrate bonding apparatus a first chucking stage includes a first stage base, a plurality of first cylindrical members, and a plurality of first drive mechanisms. The first stage base includes a first main face facing a second chucking stage. The plurality of first cylindrical members are disposed on the first main face. The plurality of first cylindrical members are arrayed in planar directions. The plurality of first cylindrical members protrudes from the first main face in a direction toward the second chucking stage to chuck the first substrate. The plurality of first drive mechanisms are configured to drive the plurality of first cylindrical members independently of each other. The substrate bonding apparatus further comprises a first pressure control mechanism configured to control pressure states of spaces in the plurality of first cylindrical members independently of each other.Type: ApplicationFiled: March 12, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Hironobu TAMURA, Yoshiharu ONO
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Publication number: 20200258793Abstract: According to one embodiment, a liquid delivery member is provided which is to be arranged at a predetermined distance from a processing object, and which is configured to deliver a liquid from a slit while the liquid delivery member and the processing object are caused to make relative displacement therebetween in a first direction. The liquid delivery member includes a delivery amount adjustment part provided on a face that forms the slit, extending in a second direction orthogonal to the first direction, and configured to adjust a delivery amount of the liquid.Type: ApplicationFiled: September 4, 2019Publication date: August 13, 2020Applicant: Toshiba Memory CorporationInventors: Hironobu TAMURA, lkuo YONEDA, Yoshiharu ONO
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Publication number: 20190244809Abstract: A chemical liquid application apparatus of an embodiment is a chemical liquid application apparatus that applies a chemical liquid to a substrate and removes the chemical liquid on an edge of the substrate by a predetermined width in a state where the substrate is being rotated by a spinner. The chemical liquid application apparatus includes a detection unit that detects a position of a mark on the substrate, a transfer unit that transfers the substrate onto the spinner, and a control unit that calculates a center position of a shot map from the position of the mark and controls the transfer unit to cause the center position of the shot map to coincide with a rotating center of the spinner when the transfer unit transfers the substrate onto the spinner.Type: ApplicationFiled: August 17, 2018Publication date: August 8, 2019Applicant: Toshiba Memory CorporationInventor: Yoshiharu ONO
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Patent number: 10192741Abstract: According to one embodiment, a device substrate includes a multilayer film that includes a film constituting a device element and is disposed on a substrate. A main face on which the device element is disposed includes a patterning region on which a resist is to be applied during an imprint process, and a bevel region provided as a region from a peripheral edge portion of the patterning region to an end portion of the device substrate. The bevel region includes a region where an upper surface of the bevel region becomes lower toward the end portion of the device substrate relative to an upper surface of the patterning region. The upper surface of the bevel region has an inclination angle of 10° or more and 90° or less with respect to the upper surface of the patterning region, at a boundary between the patterning region and the bevel region.Type: GrantFiled: September 6, 2017Date of Patent: January 29, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takahito Nishimura, Yoshihisa Kawamura, Kazuhiro Takahata, Ikuo Yoneda, Yoshiharu Ono
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Publication number: 20170365470Abstract: According to one embodiment, a device substrate includes a multilayer film that includes a film constituting a device element and is disposed on a substrate. A main face on which the device element is disposed includes a patterning region on which a resist is to be applied during an imprint process, and a bevel region provided as a region from a peripheral edge portion of the patterning region to an end portion of the device substrate. The bevel region includes a region where an upper surface of the bevel region becomes lower toward the end portion of the device substrate relative to an upper surface of the patterning region. The upper surface of the bevel region has an inclination angle of 10° or more and 90° or less with respect to the upper surface of the patterning region, at a boundary between the patterning region and the bevel region.Type: ApplicationFiled: September 6, 2017Publication date: December 21, 2017Applicant: Toshiba Memory CorporationInventors: Takahito NISHIMURA, Yoshihisa KAWAMURA, Kazuhiro TAKAHATA, lkuo YONEDA, Yoshiharu ONO
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Patent number: 9793120Abstract: According to one embodiment, a device substrate includes a multilayer film that includes a film constituting a device element and is disposed on a substrate. A main face on which the device element is disposed includes a patterning region on which a resist is to be applied during an imprint process, and a bevel region provided as a region from a peripheral edge portion of the patterning region to an end portion of the device substrate. The bevel region includes a region where an upper surface of the bevel region becomes lower toward the end portion of the device substrate relative to an upper surface of the patterning region. The upper surface of the bevel region has an inclination angle of 10° or more and 90° or less with respect to the upper surface of the patterning region, at a boundary between the patterning region and the bevel region.Type: GrantFiled: January 29, 2016Date of Patent: October 17, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takahito Nishimura, Yoshihisa Kawamura, Kazuhiro Takahata, Ikuo Yoneda, Yoshiharu Ono
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Publication number: 20160372333Abstract: According to one embodiment, a device substrate includes a multilayer film that includes a film constituting a device element and is disposed on a substrate. A main face on which the device element is disposed includes a patterning region on which a resist is to be applied during an imprint process, and a bevel region provided as a region from a peripheral edge portion of the patterning region to an end portion of the device substrate. The bevel region includes a region where an upper surface of the bevel region becomes lower toward the end portion of the device substrate relative to an upper surface of the patterning region. The upper surface of the bevel region has an inclination angle of 10° or more and 90° or less with respect to the upper surface of the patterning region, at a boundary between the patterning region and the bevel region.Type: ApplicationFiled: January 29, 2016Publication date: December 22, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Takahito NISHIMURA, Yoshihisa KAWAMURA, Kazuhiro TAKAHATA, Ikuo YONEDA, Yoshiharu ONO
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Publication number: 20150311729Abstract: There is provided a charging device which can rapidly charge, with a single charger, portable devices of a plurality of charging specifications. A plurality of available power indicating circuits included in a USB module 10 notify, through a data line, a portable device coupled to the charging device of a signal indicating suppliable amount of current. A CPU 4 obtains, from a portable device coupled thereto, information identifying the portable device, at the time of adjustment. A memory 6 has a table stored therein, for a plurality of portable devices, defining a correspondence between information identifying a portable device and an available power indicating circuit. Referring to the table based on the obtained information, the CPU 4 selects an available power indicating circuit and, at the time of actual operation, activates only the selected available power indicating circuit.Type: ApplicationFiled: July 7, 2015Publication date: October 29, 2015Inventors: Yoshiharu Ono, Tsutomu Tanaka, Mamoru Mochizuki, Takashi Makita
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Patent number: 9153984Abstract: There is provided a charging device which can rapidly charge, with a single charger, portable devices of a plurality of charging specifications. A plurality of available power indicating circuits included in a USB module 10 notify, through a data line, a portable device coupled to the charging device of a signal indicating suppliable amount of current. A CPU 4 obtains, from a portable device coupled thereto, information identifying the portable device, at the time of adjustment. A memory 6 has a table stored therein, for a plurality of portable devices, defining a correspondence between information identifying a portable device and an available power indicating circuit. Referring to the table based on the obtained information, the CPU 4 selects an available power indicating circuit and, at the time of actual operation, activates only the selected available power indicating circuit.Type: GrantFiled: February 20, 2013Date of Patent: October 6, 2015Assignee: Renesas Electronics CorporationInventors: Yoshiharu Ono, Tsutomu Tanaka, Mamoru Mochizuki, Takashi Makita
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Patent number: 8671773Abstract: An electronic flow meter includes a magnetic sensor, phase-A and phase-B drivers, a phase-A comparator, a phase-B comparator, a two-phase encoder, and a rotational speed timer. The two-phase encoder determines a normal/reverse direction where the impeller is rotated based on event signals sampled by the phase-A and the phase-B comparators, respectively, causing a counter to count up or to count down according to the normal/reverse direction as determined, thereby outputting an event count signal. The rotational speed timer calculates a rotational frequency of the impeller from the event count signal outputted by the two-phase encoder and sets frequencies of respective sampling signals of the phase-A and the phase-B comparators at a time when the rotational frequency of the impeller is measured next, and respective drive periods of the phase-A and the phase-B drivers in accordance with the rotational frequency of the impeller as calculated.Type: GrantFiled: May 29, 2012Date of Patent: March 18, 2014Assignee: Renesas Electronics CorporationInventors: Yoshiharu Ono, Osamu Karino, Yoshihiro Shimizu, Yoshihiro Miyagawa, Hiroyuki Kawajiri, Takehiro Furukawa
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Publication number: 20130241469Abstract: There is provided a charging device which can rapidly charge, with a single charger, portable devices of a plurality of charging specifications. A plurality of available power indicating circuits included in a USB module 10 notify, through a data line, a portable device coupled to the charging device of a signal indicating suppliable amount of current. A CPU 4 obtains, from a portable device coupled thereto, information identifying the portable device, at the time of adjustment. A memory 6 has a table stored therein, for a plurality of portable devices, defining a correspondence between information identifying a portable device and an available power indicating circuit. Referring to the table based on the obtained information, the CPU 4 selects an available power indicating circuit and, at the time of actual operation, activates only the selected available power indicating circuit.Type: ApplicationFiled: February 20, 2013Publication date: September 19, 2013Applicant: Renesas Electronics CorporationInventors: Yoshiharu Ono, Tsutomu Tanaka, Mamoru Mochizuki, Takashi Makita
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Publication number: 20120304779Abstract: An electronic flow meter includes a magnetic sensor, phase-A and phase-B drivers, a phase-A comparator, a phase-B comparator, a two-phase encoder, and a rotational speed timer. The two-phase encoder determines a normal/reverse direction where the impeller is rotated based on event signals sampled by the phase-A and the phase-B comparators, respectively, causing a counter to count up or to count down according to the normal/reverse direction as determined, thereby outputting an event count signal. The rotational speed timer calculates a rotational frequency of the impeller from the event count signal outputted by the two-phase encoder and sets frequencies of respective sampling signals of the phase-A and the phase-B comparators at a time when the rotational frequency of the impeller is measured next, and respective drive periods of the phase-A and the phase-B drivers in accordance with the rotational frequency of the impeller as calculated.Type: ApplicationFiled: May 29, 2012Publication date: December 6, 2012Inventors: Yoshiharu ONO, Osamu KARINO, Yoshihiro SHIMIZU, Yoshihiro MIYAGAWA, Hiroyuki KAWAJIRI, Takehiro FURUKAWA
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Patent number: 8092703Abstract: It is an object of the present invention to provide a method of manufacturing a semiconductor device that reduces the deterioration in processed configuration and the pattern roughness of a film to be processed, and is close to the original design and applicable to a dual damascene step and the like. The manufacturing method comprises a processing mask layer forming step of forming a processing mask layer (a lower organic film and a middle layer) comprising at least one film, and hardening treatment for at least one film of the processing mask layer by applying a film and heat hardening treatment; a processing mask layer etching step of applying a resist film for exposure to the processing mask layer, exposing and developing it to form a resist pattern, and etching the processing mask layer using the resist pattern as a mask; and a film to be processed etching step of etching the film to be processed using the pattern of the processing mask layer formed at the processing mask layer etching step as a mask.Type: GrantFiled: June 12, 2007Date of Patent: January 10, 2012Assignee: Renesas Electronics CorporationInventors: Takeo Ishibashi, Kazumasa Yonekura, Masahiro Tadokoro, Kazunori Yoshikawa, Yoshiharu Ono
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Publication number: 20070287298Abstract: It is an object of the present invention to provide a method of manufacturing a semiconductor device that reduces the deterioration in processed configuration and the pattern roughness of a film to be processed, and is close to the original design and applicable to a dual damascene step and the like. The manufacturing method comprises a processing mask layer forming step of forming a processing mask layer (a lower organic film and a middle layer) comprising at least one film, and hardening treatment for at least one film of the processing mask layer by applying a film and heat hardening treatment; a processing mask layer etching step of applying a resist film for exposure to the processing mask layer, exposing and developing it to form a resist pattern, and etching the processing mask layer using the resist pattern as a mask; and a film to be processed etching step of etching the film to be processed using the pattern of the processing mask layer formed at the processing mask layer etching step as a mask.Type: ApplicationFiled: June 12, 2007Publication date: December 13, 2007Inventors: Takeo Ishibashi, Kazumasa Yonekura, Masahiro Tadokoro, Kazunori Yoshikawa, Yoshiharu Ono
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Patent number: 7066131Abstract: In the present invention, there is provided a cylinder head in which seat rings, against which are placed intake valves, are mounted respectively on a plurality of intake ports that communicate with a combustion chamber of an internal combustion engine, and, among the plurality of intake ports, an intake port on which is mounted an eccentric seat ring, with a center of an inner diameter of this eccentric seat ring being eccentric relative to a center of an outer diameter of this eccentric seat ring, is present together with an intake port on which is mounted a standard seat ring, with a center of an inner diameter of this standard seat ring matching a center of an outer diameter of this standard seat ring. As a result, a flow coefficient can be secured using the intake port on which the standard seat ring is mounted, and the swirl flow can be strengthened using the intake port on which the eccentric seat ring is mounted.Type: GrantFiled: February 13, 2002Date of Patent: June 27, 2006Assignee: Niigata Power Systems Co., Ltd.Inventors: Satoru Goto, Sadao Nakayama, Yoshiharu Ono
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Patent number: 7066164Abstract: The present invention has been realized in order to keep the cylinder exhaust temperature of a gas engine within a predetermined range, and thereby prevent the generation of misfire and knocking. In the present invention, in S1, when the number of rotations of the engine is greater than a predetermined number, in S2, the exhaust temperatures of the cylinders are sampled at predetermined intervals, in S3, an average of the exhaust temperatures is calculated, in S4, the load factor at that point is determined, in S5, the average exhaust temperature Tave is compared with the exhaust temperature T(n) of each cylinder, and it is determined whether the deviation ?Tn is greater or smaller than the set deviation Tlimit for that load factor. When the deviation ?Tn is smaller, the exhaust temperature is within the set deviation and there is no need to adjust the fuel spray period, and therefore the sequence returns to S2.Type: GrantFiled: August 29, 2002Date of Patent: June 27, 2006Assignee: Niigata Power Systems Co., Ltd.Inventors: Yoshiharu Ono, Satoru Goto, Yoshifumi Nishi, Sadao Nakayama
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Via-filling material and process for fabricating semiconductor integrated circuit using the material
Patent number: 7030007Abstract: A via-filling material includes a polymer containing a repeating unit represented by wherein R1 one of hydrogen, fluorine, chlorine, bromine, and methyl group; R2 is one of hydrogen, a C1-3 alkyl group, and a C1-4 alkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is —C(?O)O— or —S(?O)2O—. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.Type: GrantFiled: July 22, 2003Date of Patent: April 18, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Teruhiko Kumada, Toshiyuki Toyoshima, Hideharu Nobutoki, Takeo Ishibashi, Yoshiharu Ono, Junjiro Sakai