Patents by Inventor Yoshiharu Tosaka
Yoshiharu Tosaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9287857Abstract: There is provided a semiconductor device having: a latch circuit having a plurality of data holding nodes; a first capacitance element connected to the first data holding node included in the plurality of data holding nodes; and a first switch element provided between the first data holding node and the first capacitance element.Type: GrantFiled: July 22, 2014Date of Patent: March 15, 2016Assignee: SOCIONEXT INC.Inventors: Taiki Uemura, Yoshiharu Tosaka
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Publication number: 20140333363Abstract: There is provided a semiconductor device having: a latch circuit having a plurality of data holding nodes; a first capacitance element connected to the first data holding node included in the plurality of data holding nodes; and a first switch element provided between the first data holding node and the first capacitance element.Type: ApplicationFiled: July 22, 2014Publication date: November 13, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiki Uemura, Yoshiharu Tosaka
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Patent number: 8816739Abstract: There is provided a semiconductor device having: a latch circuit (103, 104) having a plurality of data holding nodes; a first capacitance element (C) connected to the first data holding node (A) included in the plurality of data holding nodes; and a first switch element (SW2) provided between the first data holding node (A) and the first capacitance element (C).Type: GrantFiled: April 22, 2010Date of Patent: August 26, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Patent number: 8803549Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.Type: GrantFiled: September 19, 2011Date of Patent: August 12, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Patent number: 8749287Abstract: A semiconductor device has a first latch circuit, a second latch circuit configured to receive an output of the first latch circuit, a first switching element provided between the first latch circuit and the second latch circuit, a feedback line for feeding data held by the second latch circuit to the first latch circuit, and a second switching element provided on the feedback line.Type: GrantFiled: August 2, 2010Date of Patent: June 10, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Patent number: 8561006Abstract: A CAD device according to the embodiments includes means that determines signal transmission time of each signal transmission circuit in an LSI circuit, means that determines an output inversion rate of a flip-flop circuit included in each signal transmission circuit when the flip-flop circuit is exposed to radiation, means that determines a signal transmission circuit that is a critical path, means that calculates a total soft error rate of the LSI circuit on the basis of the signal transmission time, the output inversion rate, and a clock period, and means that, when a predetermined soft error rate is less than the total soft error rate of the LSI circuit as a result of comparison, reducing the total soft error rate of the LSI circuit to the extent possible without changing signal transmission time of the signal transmission circuit, which is a critical path.Type: GrantFiled: March 24, 2008Date of Patent: October 15, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Patent number: 8441294Abstract: A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element.Type: GrantFiled: March 1, 2011Date of Patent: May 14, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Patent number: 8421503Abstract: A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit.Type: GrantFiled: March 2, 2010Date of Patent: April 16, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Publication number: 20120038386Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.Type: ApplicationFiled: September 19, 2011Publication date: February 16, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiki UEMURA, Yoshiharu Tosaka
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Patent number: 8072251Abstract: A latch circuit includes: four or more gates; three input terminals and one or two output terminals which are connected to at least one of the four or more gates; a feedback circuit in which respective input terminals of the four or more gates are connected to output terminals of at least another two of the four gates; and a data inverting gate which, when all data input into the three input terminals is the same, outputs inverted data of the data from the output terminals, and when all the data input into the three input terminals is not the same, retains previous data.Type: GrantFiled: February 19, 2009Date of Patent: December 6, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Patent number: 8035410Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.Type: GrantFiled: September 9, 2010Date of Patent: October 11, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Publication number: 20110148495Abstract: A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element.Type: ApplicationFiled: March 1, 2011Publication date: June 23, 2011Applicant: Fujitsu Microelectronics LimitedInventors: Taiki UEMURA, Yoshiharu TOSAKA
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Publication number: 20110006803Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.Type: ApplicationFiled: September 9, 2010Publication date: January 13, 2011Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Taiki UEMURA, Yoshiharu TOSAKA
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Publication number: 20100308881Abstract: A semiconductor device has a first latch circuit, a second latch circuit configured to receive an output of the first latch circuit, a first switching element provided between the first latch circuit and the second latch circuit, a feedback line for feeding data held by the second latch circuit to the first latch circuit, and a second switching element provided on the feedback line.Type: ApplicationFiled: August 2, 2010Publication date: December 9, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiki UEMURA, Yoshiharu TOSAKA
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Patent number: 7812630Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.Type: GrantFiled: December 2, 2008Date of Patent: October 12, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Publication number: 20100225356Abstract: A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit.Type: ApplicationFiled: March 2, 2010Publication date: September 9, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Taiki Uemura, Yoshiharu Tosaka
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Publication number: 20100213998Abstract: There is provided a semiconductor device having: a latch circuit (103, 104) having a plurality of data holding nodes; a first capacitance element (C) connected to the first data holding node (A) included in the plurality of data holding nodes; and a first switch element (SW2) provided between the first data holding node (A) and the first capacitance element (C).Type: ApplicationFiled: April 22, 2010Publication date: August 26, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiki Uemura, Yoshiharu Tosaka
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Patent number: 7719337Abstract: A semiconductor device includes a circuit having a first data holding node and a second data holding node; a first MOS field-effect transistor coupled to the first data holding node; a second MOS field-effect transistor coupled to the second data holding node; and a clock generation circuit coupled to a first gate electrode of the first MOS field-effect transistor for outputting a clock signal, wherein the first gate electrode is coupled to the second data holding node via the second MOS field-effect transistor, and a second gate electrode of the second MOS field-effect transistor is coupled to the first data holding node via the first MOS field-effect transistor.Type: GrantFiled: October 16, 2008Date of Patent: May 18, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Publication number: 20090243686Abstract: A latch circuit includes: four or more gates; three input terminals and one or two output terminals which are connected to at least one of the four or more gates; a feedback circuit in which respective input terminals of the four or more gates are connected to output terminals of at least another two of the four gates; and a data inverting gate which, when all data input into the three input terminals is the same, outputs inverted data of the data from the output terminals, and when all the data input into the three input terminals is not the same, retains previous data.Type: ApplicationFiled: February 19, 2009Publication date: October 1, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Taiki UEMURA, Yoshiharu TOSAKA
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Publication number: 20090140764Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.Type: ApplicationFiled: December 2, 2008Publication date: June 4, 2009Applicant: FUJITSU LIMITEDInventors: Taiki UEMURA, Yoshiharu Tosaka