Abstract: Certain embodiments provide an image processing apparatus including an image processing circuit configured to perform image processing on continuously captured image data frame by frame, a failure diagnosis processing circuit configured to diagnose a failure of the image processing circuit, and a failure diagnosis control circuit configured to control whether to perform failure diagnosis at an arbitrary frame.

Abstract: An image processing apparatus of an embodiment is an image processing apparatus including a first image processing section configured to perform image processing for frames which are designated as processing target frames, a failure diagnosis processing section configured to perform failure diagnosis of the first image processing section at each frame period, and a failure diagnosis control section configured to control execution of the failure diagnosis processing section. The failure diagnosis control section includes a signal selecting section that gives notice of a failure diagnosis permission state which is a state where the first image processing section is capable of executing failure diagnosis. The signal selecting section outputs a failure diagnosis start permission signal at a time point of receiving a pseudo image processing completion signal from a failure diagnosis processing start timing generating section if the input frame is a processing non-target frame.

Abstract: An image processing apparatus of an embodiment is an image processing apparatus including a first image processing section configured to perform image processing for frames which are designated as processing target frames, a failure diagnosis processing section configured to perform failure diagnosis of the first image processing section at each frame period, and a failure diagnosis control section configured to control execution of the failure diagnosis processing section. The failure diagnosis control section includes a signal selecting section that gives notice of a failure diagnosis permission state which is a state where the first image processing section is capable of executing failure diagnosis. The signal selecting section outputs a failure diagnosis start permission signal at a time point of receiving a pseudo image processing completion signal from a failure diagnosis processing start timing generating section if the input frame is a processing non-target frame.

Abstract: Certain embodiments provide an image processing apparatus including an image processing circuit configured to perform image processing on continuously captured image data frame by frame, a failure diagnosis processing circuit configured to diagnose a failure of the image processing circuit, and a failure diagnosis control circuit configured to control whether to perform failure diagnosis at an arbitrary frame.

Abstract: Certain embodiments provide an image processing apparatus including an image processing circuit configured to perform image processing on continuously captured image data frame by frame, a failure diagnosis processing circuit configured to diagnose a failure of the image processing circuit, and a failure diagnosis control circuit configured to control whether to perform failure diagnosis at an arbitrary frame.

Abstract: An image processing apparatus according to an embodiment includes an arranger, an image processor, an evaluation value calculator, and an abnormality detector. The arranger arranges a test data sequence in a blanking period of video data including an image data region in which image data is arranged and the blanking period in which the image data is not arranged. The image processor applies image processing to the test data sequence arranged in the video data and the image data. The evaluation value calculator calculates an evaluation value based on an image processing result of the test data sequence in the video data. The abnormality detector outputs a signal indicating an abnormality when the evaluation value does not fluctuate according to the predetermined order.

Abstract: Certain embodiments provide an image processing apparatus including an image processing circuit configured to perform image processing on continuously captured image data frame by frame, a failure diagnosis processing circuit configured to diagnose a failure of the image processing circuit, and a failure diagnosis control circuit configured to control whether to perform failure diagnosis at an arbitrary frame.

Abstract: A processing device includes generation circuitry, storage circuitry, and interpolation circuitry. The generation circuitry generates a first index based on a numerical value of a high-order predetermined number of digits. The converted value of the reference input value corresponding to each index obtained in the generation circuitry is beforehand stored as a look-up table in the storage circuitry. The interpolation circuitry acquires the first converted value corresponding to the first index using the look-up table. And the interpolation circuitry computes the second index that adjoins the first index by carrying out increment or decrement of the first index. Furthermore, the interpolation circuitry acquires the second converted value corresponding to the second index using the look-up table of the storage circuitry. And the interpolation circuitry computes the converted value of the input value by linearity interpolation based on the shift amount from the reference input value of the first index.

Abstract: An imaging device for tracking moving objects includes an image output device outputting first and second images that include a moving object to be tracked. A memory stores image data from the image output device. An image processing device includes local storage and performs a block matching processing comprising evaluating a first block in the first image, dividing the second image into multiple regions, storing image data for a divided region in the local storage unit, determining similarity of the first block to blocks in each of the divided regions in turn, and then determining the similarity of the first and second images according to results obtained for each of the divided regions.

Abstract: A processing device includes generation circuitry, storage circuitry, and interpolation circuitry. The generation circuitry generates a first index based on a numerical value of a high-order predetermined number of digits. The converted value of the reference input value corresponding to each index obtained in the generation circuitry is beforehand stored as a look-up table in the storage circuitry. The interpolation circuitry acquires the first converted value corresponding to the first index using the look-up table. And the interpolation circuitry computes the second index that adjoins the first index by carrying out increment or decrement of the first index. Furthermore, the interpolation circuitry acquires the second converted value corresponding to the second index using the look-up table of the storage circuitry. And the interpolation circuitry computes the converted value of the input value by linearity interpolation based on the shift amount from the reference input value of the first index.

Abstract: An image processing apparatus according to an embodiment includes an arranger, an image processor, an evaluation value calculator, and an abnormality detector. The arranger arranges a test data sequence in a blanking period of video data including an image data region in which image data is arranged and the blanking period in which the image data is not arranged. The image processor applies image processing to the test data sequence arranged in the video data and the image data. The evaluation value calculator calculates an evaluation value based on an image processing result of the test data sequence in the video data. The abnormality detector outputs a signal indicating an abnormality when the evaluation value does not fluctuate according to the predetermined order.

Abstract: An imaging device for tracking moving objects includes an image output device outputting first and second images that include a moving object to be tracked. A memory stores image data from the image output device. An image processing device includes local storage and performs a block matching processing comprising evaluating a first block in the first image, dividing the second image into multiple regions, storing image data for a divided region in the local storage unit, determining similarity of the first block to blocks in each of the divided regions in turn, and then determining the similarity of the first and second images according to results obtained for each of the divided regions.

Abstract: An image decoding apparatus obtains the prediction error or a restored image of the encoding object image by inverse processing of the encoding processing of encoded image data encoded by motion compensation predictive coding, in which a restored image is obtained by adding the prediction error and a reference image, a reduced size image of the restored image is generated and stored along with the restored image; wherein, when an image is encoded by an encoding mode that uses reference pixels that include two times or more number of pixels of a region of a predetermined number of pixels, a reference image is obtained by reading out and expanding the stored reduced size image of the restored image, and when an image is encoded using reference pixels of less than two times a number of pixels of the predetermined number of pixels, the reference image is obtained from the stored restored image.

Abstract: An input pixel valid-bit-number setting unit sets an input pixel valid-bit-number which is the number of gradations of input pixel data. A predictive pixel value generating unit refers to the higher-order bits of earlier already-input pixel data to generate a predictive pixel value for the higher-order bits of a new input pixel. A prediction error group detecting unit detects a prediction error group indicative of the magnitude range of a difference between the predictive pixel value and the value of the higher-order bits of the new input pixel. A prediction error encoding unit multiplexes variable-length encoded information indicative of the prediction error group, overhead bits indicative of a specific value within the prediction error group, and the lower-order bits of the input pixel appropriate for the input pixel valid-bit-number.

Abstract: An image compressor has an input pixel value correction unit, a predicted pixel value generation unit, an error level detection unit, a predicted error computation unit, a predicted error coding unit, a packing unit and a target code amount difference level detection unit. The predicted error coding unit encodes, by variable-length coding, group information indicating a group to which the magnitude of a predicted error belongs and added bit data indicating a particular predicted error value in the group, and performs encoding by removing less significant bit data according to a target code amount difference level in the added bit data for the predicted error if the magnitude of the predicted error is equal to or larger than a predetermined value.

Abstract: A restored image that has undergone motion compensation predictive decoding processing by an inverse conversion processing section and a motion compensation section is written for reference image use in a memory by a memory control section. The memory control section reads out a reference image that has undergone thinning out processing from the memory for use in decoding image data that has undergone bidirectional predictive coding and dual-prime predictive coding. The thinned-out reference image is interpolated and restored to a reference image required for motion compensation processing. Thus, even when the necessary maximum memory bandwidth is suppressed, the deterioration in image quality is made minute and partial.

Abstract: A decoding apparatus comprises a variable length decoder that decodes zero-run length and nonzero coefficient, an inverse quantizer that inverse-quantizes the nonzero coefficient, a zero-run reconstruction processor that reconstruct zero coefficients, a FIFO memory that store the zero-run length data and nonzero coefficients, an inverse discrete cosine transformer that subjects the coefficients to an inverse discrete cosine transformation, and a motion compensator that subjects the transformed result to a motion compensation.

Abstract: A decoding apparatus comprises a variable length decoder that decodes zero-run length and nonzero coefficient, an inverse quantizer that inverse-quantizes the nonzero coefficient, a zero-run reconstruction processor that reconstruct zero coefficients, a FIFO memory that store the zero-run length data and nonzero coefficients, an inverse discrete cosine transformer that subjects the coefficients to an inverse discrete cosine transformation, and a motion compensator that subjects the transformed result to a motion compensation.

Abstract: A motion vector detector that divides a picture which is encoded into a plurality of encoding blocks and evaluates differences between each encoding block and a reference block in a motion estimation range defined in a reference picture to detect a motion vector between pictures of a moving image.

Abstract: A decoding apparatus comprises a variable length decoder that decodes zero-run length and nonzero coefficient, an inverse quantizer that inverse-quantizes the nonzero coefficient, a zero-run reconstruction processor that reconstruct zero coefficients, a FIFO memory that store the zero-run length data and nonzero coefficients, an inverse discrete cosine transformer that subjects the coefficients to an inverse discrete cosine transformation, and a motion compensator that subjects the transformed result to a motion compensation.