Abstract: A probe includes a plurality of boards each of which has a plurality of magnets, a plurality of the boards include a first board and a second board laid on the first board, a plurality of the magnets include a plurality of first magnets provided with the first board and a plurality of second magnets provided with the second board and arranged so as to respectively face a plurality of the first magnets, and the first magnet and the second magnet facing each other are provided so that mutually different magnetic poles face each other.

Abstract: A probe comprises: a membrane having a bump which contacts an input/output terminal of an IC device built into a semiconductor wafer under test; a pitch conversion board having a bottom surface on which a first terminal is provided and a top surface on which a second terminal connected to the first terminal is provided; a circuit board which is electrically connected to a test head and has a third terminal; a first anisotropic conductive rubber member having a first conductor part which electrically connects the bump of the membrane and the first terminal of the pitch conversion board; and a second anisotropic conductive rubber member having a second conductor part which electrically connects the second terminal of the pitch conversion board and the third terminal of the circuit board, and the second conductor parts are provided on the whole of the second anisotropic conductive rubber member.

Abstract: In order to shorten testing time of a plurality of devices under test formed on a semiconductor wafer, a wafer tray used by a test apparatus performing the test is provided. The wafer tray includes a first flow passage for fixing the semiconductor wafer to the wafer tray using vacuum suction, a second flow passage for fixing the wafer tray to the test apparatus using vacuum suction, and a heater for heating a loading surface on which at least the semiconductor wafer is loaded. By using this wafer tray, the semiconductor wafer, which is the object being tested, can be smoothly attached to and detached from different test heads, and testing can be begun quickly after the semiconductor wafer is attached to a test head.

Abstract: There is provided a testing system for testing a plurality of semiconductor chips formed on a single semiconductor wafer. The testing system includes a wafer substrate, a plurality of wafer connector terminals that are provided on the wafer substrate in such a manner that one or more wafer connector terminals correspond to each of the semiconductor chips, where each wafer connector terminal is to be electrically connected to an input/output terminal of a corresponding semiconductor chip, a plurality of circuit units that are provided on the wafer substrate in such a manner that one or more circuit units corresponds to each of the semiconductor chips, where each circuit unit generates a test signal to be used for testing a corresponding semiconductor chip and supplies the test signal to the corresponding semiconductor chip to test the corresponding semiconductor chip, and a controller that generates a control signal used to control the plurality of circuit units.

Abstract: A probe apparatus includes a wire substrate with terminals; a wafer tray forming a hermetically sealed space with the wire substrate and for mounting a semiconductor wafer; a probe wafer provided between the wire substrate and the wafer tray, having an apparatus connection terminal electrically connected to a terminal of the wire substrate and wafer connection terminals electrically connected to the semiconductor chips respectively and collectively; an apparatus anisotropic conductive sheet provided between the wire substrate and the probe wafer; a wafer anisotropic conductive sheet provided between the probe wafer and the semiconductor wafer; and a decompressing section that decompresses the hermetically sealed space between the wire substrate and the wafer tray, to cause the wafer tray to move to a predetermined position from the wire substrate, to electrically connect the wire substrate and the probe wafer, and to electrically connect the probe wafer and the semiconductor wafer.

Abstract: A wafer unit for testing is electrically connected to a plurality of chips to be tested formed on a wafer to be tested, the wafer unit for testing including: a connecting wafer provided to face the wafer to be tested, and to be electrically connected to each of the plurality of chips to be tested; and a temperature distribution adjusting section provided on the connecting wafer, and to adjust a temperature distribution of the wafer to be tested.

Abstract: A probe wafer electrically connected to a semiconductor wafer on which a plurality of semiconductor chips are formed includes: a wafer substrate for pitch conversion including a wafer connection surface and an apparatus connection surface opposing the wafer connection surface; a plurality of wafer connection terminals formed on the wafer connection surface of the wafer substrate for pitch conversion, at least one wafer connection terminal provided for each of the semiconductor chips and electrically connected to an input/output terminal of the corresponding semiconductor chip; a plurality of apparatus connection terminals formed on the apparatus connection surface of the wafer substrate in one-to-one relation with the plurality of wafer connection terminals at an interval different from an interval of the wafer connection terminals, to be electrically connected to an external apparatus; and a plurality of transfer paths, each electrically connecting a corresponding wafer connection terminal to an apparatus co

Abstract: A probe includes a plurality of boards each of which has a plurality of magnets, a plurality of the boards include a first board and a second board laid on the first board, a plurality of the magnets include a plurality of first magnets provided with the first board and a plurality of second magnets provided with the second board and arranged so as to respectively face a plurality of the first magnets, and the first magnet and the second magnet facing each other are provided so that mutually different magnetic poles face each other.

Abstract: There is provided a testing system for testing a plurality of semiconductor chips formed on a single semiconductor wafer. The testing system includes a wafer substrate, a plurality of wafer connector terminals that are provided on the wafer substrate in such a manner that one or more wafer connector terminals correspond to each of the semiconductor chips, where each wafer connector terminal is to be electrically connected to an input/output terminal of a corresponding semiconductor chip, a plurality of circuit units that are provided on the wafer substrate in such a manner that one or more circuit units corresponds to each of the semiconductor chips, where each circuit unit generates a test signal to be used for testing a corresponding semiconductor chip and supplies the test signal to the corresponding semiconductor chip to test the corresponding semiconductor chip, and a controller that generates a control signal used to control the plurality of circuit units.

Abstract: A probe comprises: a membrane having a bump which contacts an input/output terminal of an IC device built into a semiconductor wafer under test; a pitch conversion board having a bottom surface on which a first terminal is provided and a top surface on which a second terminal connected to the first terminal is provided; a circuit board which is electrically connected to a test head and has a third terminal; a first anisotropic conductive rubber member having a first conductor part which electrically connects the bump of the membrane and the first terminal of the pitch conversion board; and a second anisotropic conductive rubber member having a second conductor part which electrically connects the second terminal of the pitch conversion board and the third terminal of the circuit board, and the second conductor parts are provided on the whole of the second anisotropic conductive rubber member.

Abstract: A probe wafer electrically connected to a semiconductor wafer on which a plurality of semiconductor chips are formed includes: a wafer substrate for pitch conversion including a wafer connection surface and an apparatus connection surface opposing the wafer connection surface; a plurality of wafer connection terminals formed on the wafer connection surface of the wafer substrate for pitch conversion, at least one wafer connection terminal provided for each of the semiconductor chips and electrically connected to an input/output terminal of the corresponding semiconductor chip; a plurality of apparatus connection terminals formed on the apparatus connection surface of the wafer substrate in one-to-one relation with the plurality of wafer connection terminals at an interval different from an interval of the wafer connection terminals, to be electrically connected to an external apparatus; and a plurality of transfer paths, each electrically connecting a corresponding wafer connection terminal to an apparatus co

Abstract: A wafer unit for testing is electrically connected to a plurality of chips to be tested formed on a wafer to be tested, the wafer unit for testing including: a connecting wafer provided to face the wafer to be tested, and to be electrically connected to each of the plurality of chips to be tested; and a temperature distribution adjusting section provided on the connecting wafer, and to adjust a temperature distribution of the wafer to be tested.

Abstract: A probe apparatus includes a wire substrate with terminals; a wafer tray forming a hermetically sealed space with the wire substrate and for mounting a semiconductor wafer; a probe wafer provided between the wire substrate and the wafer tray, having an apparatus connection terminal electrically connected to a terminal of the wire substrate and wafer connection terminals electrically connected to the semiconductor chips respectively and collectively; an apparatus anisotropic conductive sheet provided between the wire substrate and the probe wafer; a wafer anisotropic conductive sheet provided between the probe wafer and the semiconductor wafer; and a decompressing section that decompresses the hermetically sealed space between the wire substrate and the wafer tray, to cause the wafer tray to move to a predetermined position from the wire substrate, to electrically connect the wire substrate and the probe wafer, and to electrically connect the probe wafer and the semiconductor wafer.

Abstract: In order to shorten testing time of a plurality of devices under test formed on a semiconductor wafer, a wafer tray used by a test apparatus performing the test is provided. The wafer tray includes a first flow passage for fixing the semiconductor wafer to the wafer tray using vacuum suction, a second flow passage for fixing the wafer tray to the test apparatus using vacuum suction, and a heater for heating a loading surface on which at least the semiconductor wafer is loaded. By using this wafer tray, the semiconductor wafer, which is the object being tested, can be smoothly attached to and detached from different test heads, and testing can be begun quickly after the semiconductor wafer is attached to a test head.

Abstract: There is provided a testing apparatus for testing a device under test, wherein the testing apparatus is provided with a timing generator for generating a timing signal indicating the timing at which a test signal is applied; a plurality of timing delay units for delaying the timing signal; a plurality of drivers for applying the delayed test signals; a sampler for sampling the test signal and outputting a sample voltage; a comparator for outputting a comparison result indicating whether the sample voltage is higher than the reference voltage; a determination part for determining whether the sample voltage matches the reference voltage; and a timing calibration part for calibrating the delay time caused in the timing signal by the plurality of timing delay units in order to synchronize the timing at which the test signals are applied to the device under test.

Abstract: A temperature compensation circuit for effectively compensating the difference of a switching timing due to temperature change of a switching element included in a logic circuit is provided. The temperature compensation circuit includes a temperature detecting section for detecting a value corresponding to the temperature of the switching element, and a correction section for correcting the voltage of a logic signal inputted from a previous circuit to the logic circuit in order to reduce the difference of the switching timing due to the temperature change of the switching element based on the value corresponding to the temperature.

Abstract: A temperature compensation circuit for effectively compensating the difference of a switching timing due to temperature change of a switching element included in a logic circuit is provided. The temperature compensation circuit includes a temperature detecting section for detecting a value corresponding to the temperature of the switching element, and a correction section for correcting the voltage of a logic signal inputted from a previous circuit to the logic circuit in order to reduce the difference of the switching timing due to the temperature change of the switching element based on the value corresponding to the temperature.

Abstract: A sampling circuit for compensating the phase difference of a sampling pulse due to a temperature variation to accurately sample input signals is provided. The sampling circuit samples received input signals. The sampling circuit includes a pulse generator for generating a pulse signal according to a timing at which an input signal should be sampled, a step recovery diode for outputting a sampling pulse responsive to the pulse signal, a detector for detecting the value for the input signal according to the sampling pulse, a temperature detecting circuit for detecting the temperature around the step recovery diode and a temperature compensating unit for controlling a timing at which the step recovery diode outputs the sampling pulse based on the temperature detected by the temperature detecting circuit.

Abstract: There is provided a testing apparatus for testing a device under test, wherein the testing apparatus is provided with a timing generator for generating a timing signal indicating the timing at which a test signal is applied; a plurality of timing delay units for delaying the timing signal; a plurality of drivers for applying the test signals; a sampler for sampling the test signal and outputting a sample voltage; a comparator for outputting a comparison result indicating whether the sample voltage is higher than the reference voltage; a determination part for determining whether the sample voltage matches the reference voltage; and a timing calibration part for calibrating the delay time caused in the timing signal by the plurality of timing delay units in order to synchronize the timing at which the test signals are applied to the device under test.

Abstract: A sampling circuit for compensating the phase difference of a sampling pulse due to a temperature variation to accurately sample input signals is provided. The sampling circuit samples received input signals. The sampling circuit includes a pulse generator for generating a pulse signal according to a timing at which an input signal should be sampled, a step recovery diode for outputting a sampling pulse responsive to the pulse signal, a detector for detecting the value for the input signal according to the sampling pulse, a temperature detecting circuit for detecting the temperature around the step recovery diode and a temperature compensating unit for controlling a timing at which the step recovery diode outputs the sampling pulse based on the temperature detected by the temperature detecting circuit.