Abstract: The purpose of the present invention is to decrease a leak current of a voltage supply circuit using a MOS transistor. This voltage supply circuit comprises an n-channel MOS transistor having a low threshold voltage, the drain of which is connected to the power supply voltage, and a p-channel MOS transistor, the source of which is connected to the source of the n-channel MOS transistor and which supplies a voltage vii from the drain to a load circuit. Since a voltage V gs=1 V is applied to the gate-sources of the p-channel MOS transistor when said circuit is on standby, the p-channel MOS transistor operates in a larger cut-off region than an ordinary cut-off region.

Abstract: The purpose of the present invention is to decrease a leak current of a voltage supply circuit using a MOS transistor. This voltage supply circuit comprises an n-channel MOS transistor having a low threshold voltage, the drain of which is connected to the power supply voltage, and a p-channel MOS transistor, the source of which is connected to the source of the n-channel MOS transistor and which supplies a voltage vii from the drain to a load circuit. Since a voltage V gs=1 V is applied to the gate-sources of the p-channel MOS transistor when said circuit is on standby, the p-channel MOS transistor operates in a larger cut-off region than an ordinary cut-off region.

Abstract: A memory cell array is partitioned into a plurality of memory regions each of which includes a plurality of sense amplifiers and each of which is established as a unit of data input/output. Dummy regions each are formed between every two memory regions and include dummy bit lines that are set to a predetermined voltage at least during the operation of the memory cell array. Since the dummy bit lines are wired between the bit lines of the two adjacent memory regions, the voltage change in the bit lines in any of the memory regions can be prevented from affecting the bit lines in the other memory regions. As a result, malfunction of semiconductor memories can be prevented.

Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

Abstract: A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

Abstract: A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

Abstract: A memory cell array is partitioned into a plurality of memory regions each of which includes a plurality of sense amplifiers and each of which is established as a unit of data input/output. Dummy regions each are formed between every two memory regions and include dummy bit lines that are set to a predetermined voltage at least during the operation of the memory cell array. Since the dummy bit lines are wired between the bit lines of the two adjacent memory regions, the voltage change in the bit lines in any of the memory regions can be prevented from affecting the bit lines in the other memory regions. As a result, malfunction of semiconductor memories can be prevented.

Abstract: An external command receiving circuit receives an external command signal supplied from the exterior, in synchronization with one transition edge of a first clock signal. An internal command receiving circuit receives an internal command signal internally generated, in synchronization with the other transition edge of the first clock signal. Namely, receiving operation of the internal command signal by the internal command receiving circuit shifts from that of the external command signal by the external command receiving circuit by at least a half cycle of the first clock signal. Immediately after starting an operation according to the external command signal, a control circuit for operating an internal circuit does not receive an operation request according to the internal command signal. This can prevent conflict in operation between the internal circuit according to the external command signal and the internal circuit according to the internal command signal, and also prevent malfunction.

Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

Abstract: An external command receiving circuit receives an external command signal supplied from the exterior, in synchronization with one transition edge of a first clock signal. An internal command receiving circuit receives an internal command signal internally generated, in synchronization with the other transition edge of the first clock signal. Namely, receiving operation of the internal command signal by the internal command receiving circuit shifts from that of the external command signal by the external command receiving circuit by at least a half cycle of the first clock signal. Immediately after starting an operation according to the external command signal, a control circuit for operating an internal circuit does not receive an operation request according to the internal command signal. This can prevent conflict in operation between the internal circuit according to the external command signal and the internal circuit according to the internal command signal, and also prevent malfunction.

Abstract: A resetting circuit includes first and second transistors that respectively receive first and second voltages through gates. The ratio W/L of the second transistor is larger than that of the first transistor. The first and second voltages rise in accordance with the rise of a supply voltage. The second voltage is lower than the first voltage. Since an increase in the current IDS of the first transistor is greater than an increase in the current IDS of the second transistor, an inversion occurs between the current IDSs of the first and second transistors by applying a predetermined supply voltage. Since a reset signal is generated when the values of the currents IDS of the first and second transistors cross, the reset signal can always be generated by the predetermined supply voltage, independent from the threshold voltage of the transistor.

Abstract: A resetting circuit includes first and second transistors that respectively receive first and second voltages through gates. The ratio W/L of the second transistor is larger than that of the first transistor. The first and second voltages rise in accordance with the rise of a supply voltage. The second voltage is lower than the first voltage. Since an increase in the current IDS of the first transistor is greater than an increase in the current IDS of the second transistor, an inversion occurs between the current IDSs of the first and second transistors by applying a predetermined supply voltage. Since a reset signal is generated when the values of the currents IDS of the first and second transistors cross, the reset signal can always be generated by the predetermined supply voltage, independent from the threshold voltage of the transistor.

Abstract: A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.

Abstract: A semiconductor integrated circuit is adapted to make invalid an external clock, externally supplied to the semiconductor integrated circuit, when the semiconductor integrated circuit is set in an active power-down state. The semiconductor integrated circuit includes a delay locked loop DLL circuit which outputs an internal clock which phase is synchronized to the external clock. A latch circuit retains control signals in synchronism with the internal clock output by the DLL circuit. An internal circuit performs a predetermined process based on the control signals supplied from the latch circuit.

Abstract: An electromagnetic relay includes a coil wound around a core both of whose ends project therefrom. A yoke extends parallel thereto, and each of its ends is formed with two pole pieces which extend towards and lie one on each side of an end of the core with a certain gap being defined therebetween. A connecting member extends parallel to the core and the yoke and is mounted so as to be movable transversely, and means are provided for establishing and breaking some electrical connection according to such transverse movement. There are provided two armature pieces, one for each end of the core and both fixed to the connecting member. Each armature piece includes a permanent magnet plate and two plates of magnetic material fixed to it so as generally to form a C shape with one of the magnetic material plates being magnetized to be a north pole and the other a south pole.

Abstract: A high frequency R-F switch includes a switch body or housing made from a conductive material or a non-conductive resin having a conductive layer plated on the body surfaces. The switching device includes a first external connector, a first conductor having a switching contact member connected to the first external connector for switching a connection with the switch contact member. A conductive housing supports the first conductor, a second external connector and second conductor. The switch body or housing is in electrical connection with the second external conductor.

Abstract: A polarized electromagnetic device is disclosed having a generally I-shaped magnetic core member, a coil which is wound on the center portion of the core member, a pair of permanent magnets which are arranged in parallel with and outside of the respective end portions of the core member, and mutually confronting first and second armature plate members which are joined together through the pair of permanent magnets, with each magnet at the opposite end portions of the armature plate members in order to provide a spacing for accommodating the core member between the armature plate members, and consequently leaving a gap for relative movement therein. The core member and armature plate members are supported to be swingable relative to each other for movement about a center transverse axis of the center portion of the core member.

Abstract: An electromagnetic relay comprising a flat electromagnet, a movable plate member having on a lower surface a plurality of projections and a contact circuit device as stacked up together, said contact circuit device including a plurality of contact switching members each of which consists of a single movable blade and a single stationary contact, said movable blade being biased by the projections in accordance with their movement so as to provide a switching operation in cooperation with the corresponding stationary contact.

Abstract: A miniaturized electromagnetic device is disclosed, which is applicable to an electromagnetic relay of the flat package type.The electromagnetic device comprises a magnetic core having the configuration of the capital letter H, a coil wound round the magnetic core, and a pair of magnetic members for alternatingly forming two closed magnetic circuits in cooperation with said magnetic core, said magnetic members being formed in one-piece with the aid of connecting members of non-magnetic material, one of said magnetic members including a permanent magnet, and each tip of said magnetic member confronting the corresponding tip of said magnetic core and the clearance therebetween being changeable by the magnetic force generated therebetween as said coil is energized.

Abstract: A high frequency R-F switch includes a switch body of housing made from a conductive material or a non-conductive resin having a conductive layer plated on the body surfaces. The switching device includes a first external connector, a first conductor having a switching contact member connected to the first external connector for switching a connection with the switch contact member. A conductive housing .[.supports.]. .Iadd.houses .Iaddend.the first conductor, .Iadd.and connects to .Iaddend.a second external connector and second conductor. The switch body or housing is in electrical connection with the second external conductor.