Abstract: A buffer stage includes a first transistor having a control terminal connected to an output terminal of an operational amplifier and a second transistor connected in series to a main energization path of the first transistor. An overcurrent controlling circuit is configured to apply an output voltage of the operational amplifier to the control terminal of the first transistor and allow a normal operation of the first transistor when an energization current of a main energization path of an output transistor detected by an overcurrent detection transistor is less than a predetermined value, and is configured to control the output voltage of the operational amplifier to a predetermined control voltage according to a current flowing in a main energization path of the overcurrent detection transistor when the energization current of the main energization path of the output transistor is equal to or greater than the predetermined value.

Abstract: A buffer stage includes a first transistor having a control terminal connected to an output terminal of an operational amplifier and a second transistor connected in series to a main energization path of the first transistor. An overcurrent controlling circuit is configured to apply an output voltage of the operational amplifier to the control terminal of the first transistor and allow a normal operation of the first transistor when an energization current of a main energization path of an output transistor detected by an overcurrent detection transistor is less than a predetermined value, and is configured to control the output voltage of the operational amplifier to a predetermined control voltage according to a current flowing in a main energization path of the overcurrent detection transistor when the energization current of the main energization path of the output transistor is equal to or greater than the predetermined value.

Abstract: A semiconductor storage device includes a memory cell, a switch, a source driver, a drain driver, a voltage measurement circuit and a control electrode driver. The memory cell has a control electrode, a floating electrode, a source and a drain. In a writing to the memory cell, the voltage measurement circuit measures a voltage generated between the control electrode and the source when the switch is in an on state connecting the control electrode and the drain and a predetermined current flows from the current source to the memory cell, and the control electrode driver applies to the control electrode a voltage that is controlled based on the voltage measured by the voltage measurement circuit.

Abstract: A semiconductor storage device includes a memory cell, a switch, a source driver, a drain driver, a voltage measurement circuit and a control electrode driver. The memory cell has a control electrode, a floating electrode, a source and a drain. In a writing to the memory cell, the voltage measurement circuit measures a voltage generated between the control electrode and the source when the switch is in an on state connecting the control electrode and the drain and a predetermined current flows from the current source to the memory cell, and the control electrode driver applies to the control electrode a voltage that is controlled based on the voltage measured by the voltage measurement circuit.

Abstract: In a non-volatile semiconductor memory device, a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the array cell side to a voltage, and a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the reference cell side to a voltage. Constant current circuits supply an offset current. Thus, a difference between two input voltages of a differential amplifier increases.

Abstract: In the non-volatile semiconductor memory device, for a current mirror for reading out data of a memory cell, a diode-connected transistor and a cut transistor are provided. The diode-connected transistor makes a precharged voltage level lower than a power supply voltage level. The cut transistor reduces current consumption.

Abstract: The invention provides a semiconductor memory capable of realizing an efficient use of a memory area and reducing manufacturing costs. A memory has a memory cell array comprising a matrix of cells for electrically storing data. The memory cell array is divided into a plurality of block areas. Each block area is set to a four-valued area for recording the data as four-valued data or a binary area for recording the data as binary data. On an access to a memory cell (writing or reading of the data), a word line voltage for writing or a sense amplifier for reading is switched in accordance with whether the data to be accessed is the binary data or the four-valued data.

Abstract: A signal amplification circuit according to the present invention includes a current comparison part for generating a voltage in accordance with the difference between the reference current and the memory cell current at the first node and an output level setting part for generating an output signal,at the second node. The output level setting part has the first transistor for supplying a constant current in accordance with the control voltage from the power supply node to the second node and the second transistor for allowing the current in accordance with the voltage of the node to flow from the second node to the ground node. The current which flows through the second transistor is designed to be in balance with the constant current under the condition where the reference current and the memory cell current are in balance.

Abstract: A signal amplification circuit according to the present invention includes a current comparison part for generating a voltage in accordance with the difference between the reference current and the memory cell current at the first node and an output level setting part for generating an output signal at the second node. The output level setting part has the first transistor for supplying a constant current in accordance with the control voltage from the power supply node to the second node and the second transistor for allowing the current in accordance with the voltage of the node to flow from the second node to the ground node. The current which flows through the second transistor is designed to be in balance with the constant current under the condition where the reference current and the memory cell current are in balance.

Abstract: In the non-volatile semiconductor memory device, for a current mirror for reading out data of a memory cell, a diode-connected transistor and a cut transistor are provided. The diode-connected transistor makes a precharged voltage level lower than a power supply voltage level. The cut transistor reduces current consumption.

Abstract: In a non-volatile semiconductor memory device, a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the array cell side to a voltage, and a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the reference cell side to a voltage. Constant current circuits supply an offset current. Thus, a difference between two input voltages of a differential amplifier increases.

Abstract: The invention provides a semiconductor memory capable of realizing an efficient use of a memory area and reducing manufacturing costs. A memory has a memory cell array comprising a matrix of cells for electrically storing data. The memory cell array is divided into a plurality of block areas. Each block area is set to a four-valued area for recording the data as four-valued data or a binary area for recording the data as binary data. On an access to a memory cell (writing or reading of the data), a word line voltage for writing or a sense amplifier for reading is switched in accordance with whether the data to be accessed is the binary data or the four-valued data.

Abstract: In an inverter, each source of first to third P-channel MOS transistors is connected to a line of a source potential, a drain of the first P-channel MOS transistor is connected to an output node, each of first and second fuses is connected between each drain of the second and third P-channel MOS transistors and the output node, an N-channel MOS transistor is connected between the output node and a ground potential line, and each gate of these four MOS transistors is connected to an input node. At least one of the first and second fuses is blown out, and thereby, it is possible to reduce a threshold potential voltage of the inverter.

Abstract: A data transfer system has an address bus and a data bus, each divided into two parts by a bus switch. A microprocessor and program memory are connected to the first parts of the address and data buses. A data memory, data transfer controller, and input/output devices are connected to the second parts of tile address and data buses. While the microprocessor is fetching an instruction from the program memory, the bus switches disconnect the two parts of the buses, enabling the data transfer controller to transfer data directly between the data memory and input/output devices. At other times the bus switches connect the two parts of the buses, enabling the microprocessor to access the data memory and Input/output devices.