Patents by Inventor Yoshihide Kanakubo

Yoshihide Kanakubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030169026
    Abstract: The present invention provides a PWM switching regulator circuit capable of reducing power consumption while it is operated under a light load. When load condition is changed from a heavy load to a light load, an internal oscillation frequency is changed from a first oscillation frequency to a second oscillation frequency lower than the first oscillation frequency, while when the load condition is changed from the light load to the heavy load, the internal oscillation frequency is returned from the second oscillation frequency back to the first oscillation frequency in accordance with an ON/OFF ratio of a signal used to control a switch of a PWM switching regulator circuit.
    Type: Application
    Filed: January 30, 2003
    Publication date: September 11, 2003
    Inventors: Yoshihide Kanakubo, Atsuo Fukui
  • Publication number: 20030154456
    Abstract: To provide a resistor circuit with which a resistance ratio among voltage division resistors in a semiconductor integrated circuit can be realized with high accuracy. The resistor circuit of the present invention includes: a reference resistor portion; and a resistor portion including resistor elements and fuse connected in parallel with the resistor elements, respectively, for trimming the resistor elements. The resistor elements are put to be arranged in order from the resistor element having a largest resistance value so as to be adjacent to the reference resistor portion in the periphery of the reference resistor portion. As a result, it is possible to obtain accurately the ratio between a resistance value of a reference resistor and a desired resistance value determined with the ratio from the resistance value of the reference resistor.
    Type: Application
    Filed: October 9, 2002
    Publication date: August 14, 2003
    Inventors: Toshiyuki Koike, Yoshihide Kanakubo, Minoru Ariyama
  • Patent number: 6580253
    Abstract: A boosting and step-down switching regulator includes one error amplifying circuit, and an output of the error amplifying circuit is compared with a triangular wave for boosting and a triangular wave for step-down different in voltage level from each other but synchronous with each other in comparison circuits, respectively, to switch the boosting operation and the step-down operation over to each other. Thus, the boosting operation and the step-down operation can be readily switched over to each other irrespective of an input voltage and an output voltage.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: June 17, 2003
    Assignees: Seiko Instruments Inc., Device Engineering Co.
    Inventors: Yoshihide Kanakubo, Tomohiro Oka, Takeshi Naka
  • Publication number: 20030052654
    Abstract: A boosting and step-down switching regulator includes one error amplifying circuit, and an output of the error amplifying circuit is compared with a triangular wave for boosting and a triangular wave for step-down different in voltage level from each other but synchronous with, each other in comparison circuits, respectively, to switch the boosting operation and the step-down operation over to each other. Thus, the boosting operation and the step-down operation can be readily switched over to each other irrespective of an input voltage and an output voltage.
    Type: Application
    Filed: August 6, 2002
    Publication date: March 20, 2003
    Inventors: Yoshihide Kanakubo, Tomohiro Oka, Takeshi Naka
  • Patent number: 6469480
    Abstract: A voltage regulator circuit comprises a reference voltage circuit for generating a reference voltage, an error amplifying circuit for receiving the reference voltage from the reference voltage circuit and comparing the reference voltage with a given voltage resulting from dividing the output voltage of an output terminal by a pair of resistors connected in series, and an output transistor portion having two or more switchable transistors different in driving capability. A switching circuit drives a selected one of the switchable transistors in accordance with a result of the comparison by the error amplifying circuit to thereby limit overshoot of the output voltage.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: October 22, 2002
    Assignee: Seiko Instruments Inc.
    Inventor: Yoshihide Kanakubo
  • Patent number: 6469405
    Abstract: A constant-current FET functions as a constant current element by application of a constant voltage to the gate thereof. A first switch FET is disposed between the constant-current FET and a power supply without another switching element being disposed between the constant current FET and an output terminal. A second switch FET that performs an on/off operation in association with an on/off operation performed by the first switch FET is connected between the output terminal and ground.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: October 22, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Yasuhiro Moya, Tatsuya Kitta, Yoshihide Kanakubo, Tadao Akamine
  • Patent number: 6359639
    Abstract: A thermal head driving integrated circuit capable of preventing the lowering of data transfer speed, and in which the number of bonding pads can be reduced as well as current consumption has a driver circuit in which at least two shift registers are series-arranged in front and rear stages to sequentially transfer print data in a serial signal manner to be read out in a batch mode to drive a plurality of heating resistive elements. A switch circuit is interposed between an output terminal of the front-staged shift register and an input terminal of the rear-staged shift register to selectively connect and disconnect the two shift registers.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: March 19, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Tatsuya Kitta, Yoshihide Kanakubo, Yasuhiro Moya, Kazutoshi Ishii, Sumitaka Gotou
  • Patent number: 6346960
    Abstract: A thermal head driving integrated circuit may be used to perform an “n” color or “n” gradation printing operation with a simplified circuit having a reduced size by employing a single delay element connected to a plurality of resistive heating elements. The integrated circuit has a plurality of drive units each for driving a respective one of the heating elements and each having a drive transistor for driving a respective heating element, one or more delay elements, the number of delay elements being less than “n”, for supplying delayed print data to the drive transistor, a print data storing unit for storing the print data of each of the “n” types, and a print data supplying unit for supplying print data stored in the print data storing unit to the “n” delay elements.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: February 12, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshihide Kanakubo, Yasuhiro Moya, Tatsuya Kitta, Kazutoshi Ishii, Sumitaka Goto
  • Publication number: 20010026149
    Abstract: When a power supply of a voltage regulator turns on, and when a load rapidly fluctuates, overshoot occurring at an output terminal voltage is reduced by using an output transistor lower in driving capability.
    Type: Application
    Filed: February 7, 2001
    Publication date: October 4, 2001
    Inventor: Yoshihide Kanakubo
  • Patent number: 6134136
    Abstract: Reducing the chip area while improving the manufacturing efficiency as well as reducing costs in a semiconductor integrated circuit device such as a thermal head driver IC. A plurality of terminal electrodes were provided within an external data input/output circuit with an input terminal and output terminal being electrically connected to each other. In addition, an input/output protection circuit was provided to a respective one of such plurality of terminal electrodes with the input terminal and output terminal electrically connected together.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: October 17, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Kazutoshi Ishii, Sumitaka Gotou, Yasuhiro Moya, Yoshihide Kanakubo, Tatuya Kitta
  • Patent number: 6107128
    Abstract: Since a field effect MOS transistor can be formed with a reduced number of manufacturing processes, a semiconductor integrated circuit device can be materialized at a low cost. A semiconductor device has a structure in which a gate electrode is provided in the vicinity of the surface of a semiconductor substrate through a gate insulating film, a second conductive type heavily doped impurity region is provided in a region adjacent to a part of the gate electrode through a part of the gate insulating film and a part of a thick oxide film, another second conductive type heavily doped impurity region is provided in a region adjacent to an opposite part of the gate electrode opposing the part of the gate electrode through the part of the gate insulating film and a part of another thick oxide film, and a first conductive type heavily doped impurity region for device isolation is provided so as to surround the gate electrode and the second conductive type heavily doped impurity regions.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: August 22, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Kazutoshi Ishii, Sumitaka Gotou, Yasuhiro Moya, Tatsuya Kitta, Yoshihide Kanakubo