Patents by Inventor Yoshihide Minegishi

Yoshihide Minegishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135894
    Abstract: A panel drive circuit having an input interface to which an image signal is input, a gamma correction circuit that corrects an image processing signal generated by an image processing circuit performing image processing on the image signal input to the input interface, such that a gamma correction signal thus generated has predetermined gamma characteristics, an unevenness correction circuit that corrects the gamma correction signal generated through the correction by the gamma correction circuit, based on correction data for reducing unevenness of a display panel, and an D/A convertor that has a variable output voltage range, and performs D/A conversion on an unevenness correction signal generated through the correction by the unevenness correction circuit and outputs the signal thus generated to the display panel, and the unevenness correction circuit changes the correction method according to the output voltage range of the D/A convertor.
    Type: Application
    Filed: March 10, 2021
    Publication date: April 25, 2024
    Applicant: IIX INC.
    Inventors: Makoto HATAKENAKA, Takashi SAKAMOTO, Mitsuo HAGIWARA, Norimasa SENDA, Yoshihide MINEGISHI, Hiroshi MURASE
  • Publication number: 20230395038
    Abstract: An input signal correction device for reducing power consumption is compatible with a variety of display panels, and includes an input circuit, extension/degeneration circuit, separation/recovery circuit and delay adjustment circuit operating at frequency f, demura circuit operating at frequency f/2, and adder circuit.
    Type: Application
    Filed: February 25, 2021
    Publication date: December 7, 2023
    Applicant: IIX INC.
    Inventors: Makoto HATAKENAKA, Takashi SAKAMOTO, Yoshihide MINEGISHI, Ryohei HATTA, Norimasa SENDA
  • Patent number: 11823610
    Abstract: An input signal correction device includes an input circuit, extension circuit, degenerate circuit, separation circuit, recovery circuit and delay adjustment circuit that operate at an operating frequency f, demura circuit that operates at an operating frequency f/2, and adder circuit. The extension circuit extends the period of R and B input signals by a factor of 2 and outputs preprocessing signals, the degenerate circuit degenerates a G input signal, the demura circuit corrects preprocessing signals from the extension and degenerate circuits and outputs correction signals, the separation circuit reduces the period of the R and B correction signals to ½ and outputs differential signals, recovery circuit reduces the period of G correction signal to ½ and outputs the same differential signal over two periods, the delay adjustment circuit delays the input and output signals, and the adder circuit adds the differential signals to the delay signals and outputs output signals.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: November 21, 2023
    Assignee: IIX INC.
    Inventors: Makoto Hatakenaka, Takashi Sakamoto, Yoshihide Minegishi, Ryohei Hatta, Norimasa Senda