Abstract: A data-modulating apparatus for modulating data having a basic data length of m bits, to a variable-length code(d, k; m, n: r) having a basic code length of n bits. A sync signal is added to a recieved train of codes after a minimum run, the sync signal having a pattern that breaks a maximum run. The pattern is repeated twice continuously, and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in the termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

Abstract: A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

Abstract: An encoding method for encoding information bits into a codeword by a linear code is provided. The information bits appear in the codeword as a part of the codeword. The linear code is a code in which a codeword resulting from cyclically shifting an arbitrary codeword by p bit positions is also a codeword. A code polynomial having the codeword in which the information bits appear as a part thereof is computed by executing an arithmetic operation of p polynomials G0(x), . . . , Gp?1(x) and a polynomial having the information bits as coefficients. Accordingly, a quasi-cyclic (QC) code can be encoded by only polynomial operations, and an encoder can be simplified.

Abstract: A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

Abstract: A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

Abstract: A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

Abstract: A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a mniininum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

Abstract: A method and apparatus for modulating data modulates data having a length of m-bits to a variable length code having a basic code length of n-bits. A SYNC but insertion section adds a sync signal to a train of codes, after a minimum run. The sync signal has a pattern that breaks a maximum run.

Abstract: In order to reproduce data in a stable manner by correction of random and burst errors of a wide range without lowering a transfer speed, C2 error correction for correcting an inter-sector error is carried out in addition to the conventional C1 error correction for correcting an error generated in a sector. The configuration of an error correction unit (or an ECC block) including C1 and C2 codes is formed as a track. That is to say, one track is used as the base of an ECC block unit. In this way, two ECC block units never exist in the same track.

Abstract: An encoding method for encoding information bits into a codeword by a linear code is provided. The information bits appear in the codeword as a part of the codeword. The linear code is a code in which a codeword resulting from cyclically shifting an arbitrary codeword by p bit positions is also a codeword. A code polynomial having the codeword in which the information bits appear as a part thereof is computed by executing an arithmetic operation of p polynomials G0(x), . . . , Gp−1(x) and a polynomial having the information bits as coefficients. Accordingly, a quasi-cyclic (QC) code can be encoded by only polynomial operations, and an encoder can be simplified.

Abstract: A DSV bit is inserted in an input data string by a DSV bit determining insertion unit. A modulation unit has a conversion table, and the element of the conversion table comprises the element for determining uniquely, and has a conversion rule that residues obtained by dividing the number of “1” in the element of a data string and the number of “1” in the element of a code word string to be converted by 2 are identically 1 or 0 for both residues. A channel bit string is modulated according to the conversion table, and further NRZI modulated by an NRZI modulation unit. Thus, DSV control can be performed with reduced redundancy.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (y1, y2, y3). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity preserving (table I) (FIG. 1). The relations hold that m>n≧1, p≧1, and that p can vary. Preferably, m=n+1.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C) satisfying a (d,k) constraint, wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (Y1, Y2, Y2). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity preserving (table I). The relations hold that m>n≧1, p≧1, and that p can vary. Preferably, m=n+1.

Abstract: An encoder for encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal, the bitstream of the source signal being divided into smaller n-bit source words (x1, x2) which are converted by a logic circuit converter in the encoder into corresponding m-bit channel words, (y1, y2, y3). The conversion of each n-bit source word is parity preserving (see Table I and FIG. 1). The relations hold that m>n≧1, p≧1, and p can vary. Preferably, m=n+1. In order to comply with (d, k) runlength requirements, certain blocks of 2-bit source words are encoded into particular blocks of 3-bit channel words. A decoder is also disclosed for decoding a channel signal produced by the encoder.

Abstract: A demodulator refers to an internal conversion table and demodulates data that was input. Said conversion table has elements to restrict the continuation of the minimum run and a non-determined code and also has a conversion rule to take the surplus of the number of “1”s inside the elements of the data string and the number of “1”s inside the elements of the converted code word string when divided by two and then match the surplus with either a “0” or a “1”. The demodulated data is input to the DSV eliminator and output by way of the buffer after removal of the DSV bit and thus a codedword string on which DVS control was performed can be efficiently and reliably decoded.

Abstract: If there is any portion in channel bit data obtained on converting a signal read out from a recording medium into a bi-level signal which fails to satisfy a condition concerning a minimum run length or a maximum run length of the same symbol, the channel bit data is corrected to improve the bit error rate to secure a skew margin. To this end, channel bit data not satisfying a minimum run length d' of the same symbol is detected by a (d'-1) detector 4 using n-tupled clocks obtained on n-tupling channel clocks of playback data by a bit clock generator 2, where n is an integer not less than 2. A correction position of the channel bit data having the run length of the same symbol equal to (d'-1) is designated by a correction bit position designating unit 5. A data correction unit 6 then corrects the channel bit data so that the minimum run length of the same symbol will be equal to d'.

Abstract: A data encoding method for converting a (m i) bit based data word string into a (n i) bit based codeword string. The encoding method receives a (m i) bit based data word string by a shift register 1, decides a constraint length specifying the length of a data word which is to be converted by an encoder 2, and decides on which number of bits as counted from the leading end of the m bits falls the leading end bit of the data word which is to be converted. The encoding method selects, by a selector 3, one of a plurality of conversion tables constituting variable length tables and at least satisfying the minimum run length d, in accordance with the constraint length and the above results of decision. The encoding method also generates a codeword corresponding to the data word, now to be converted, in accordance with the selected conversion table.

Abstract: An audio signal transmitting apparatus including, an audio transmission signal generating unit for adding an error correction signal to a digital audio signal and encoding and interleaving the result to generate an audio transmission signal; a continuous signal generating unit which generates a continuous signal by repeating the digital control signal to be used for the reproduction of the digital audio transmission signal a predetermined number of times; a multiplexing unit for multiplexing the audio transmission signal and the continuous signal to generate a multiplexed signal; a modulated signal generating unit for modulating the multiplexed signal by a predetermined digital modulation method to generate a modulated signal within a predetermined frequency band; and an optical signal transmitting unit for converting the modulated signal to an optical transmission signal and transmitting the same.

Abstract: An 8.fwdarw.10 modulator stores a conversion table, and, when receiving 8-bit data as an address, outputs 10-bit data stored at the received address as a modulated code. The conversion table of the 8.fwdarw.10 modulator is constructed such that each NRZI-represented 10-bit data includes at least one "0.