Abstract: An information code reading device includes a processor and a memory, wherein the processor executes a program stored in the memory to: perform reading processing by using electric power supplied from an external power supply through a cable; wirelessly transmit a reading result to a predetermined external device; determine whether power supply through the cable is shut off; and perform a predetermined notification using electric power supplied from a power storage circuit element in response to determination that the power supply is shut off, the reading processing is processing for optically reading an information code, and the information code reading device comprises the power storage circuit element.

Abstract: A surgery supporting apparatus is capable of controlling a posture of a surgical instrument that is inserted into a body cavity and mechanically drivable. The apparatus includes a robot arm that can control the posture of the surgical instrument, which is attached to the robot arm via a gimbal mechanism.

Abstract: A surgery supporting apparatus capable of performing a manipulation using a surgical instrument to be inserted into a body cavity, comprises a measurement device configured to measure an insertion depth and an insertion angle, with respect to the body cavity, of a shaft of the surgical instrument inserted into the body cavity, as input of the manipulation, wherein the measurement device measures the insertion depth by measuring a sound wave propagating in a space between a transmitter attached to one of the surgical instrument and a position within a predetermined range from a position of insertion to the body cavity, and a receiver attached to the other.

Abstract: A surgery supporting apparatus is capable of controlling a posture of a first surgical instrument that is inserted into a body cavity and mechanically drivable, by using a second surgical instrument to be inserted into the body cavity. The apparatus comprises a robot arm configured to control the posture of the first surgical instrument attached to the robot arm. Instructions stored in a memory cause the apparatus to function as a control unit configured to control the motion of the robot arm such that the posture of the first surgical instrument is controlled in accordance with the posture of the second surgical instrument, in a case of a first mode, and controls the motion of the robot arm in accordance with a manipulation including contact to the robot arm, in a case of a second mode.

Abstract: A surgery assisting apparatus for controlling a posture of a first surgical tool to be inserted into a body cavity and mechanically driven, by using a second surgical tool to be inserted into the body cavity, comprises: a mode switch configured to switch a first mode and a second mode, the second surgical tool being used to control the first surgical tool in the second mode; one or more sensors configured to measure an angle and depth of insertion of a shaft of the second surgical tool into the body cavity; and at least one memory and at least one processor which function as a computing unit configured to determine a target position of a control point that is a point for specifying the posture of the first surgical tool in order to control the posture of the first surgical tool.

Abstract: A surgery supporting apparatus is capable of controlling a posture of a first surgical instrument that is inserted into a body cavity and mechanically drivable, by using a second surgical instrument to be inserted into the body cavity. The apparatus comprises a robot arm configured to control the posture of the first surgical instrument attached to the robot arm. Instructions stored in a memory cause the apparatus to function as a control unit configured to control the motion of the robot arm such that the posture of the first surgical instrument is controlled in accordance with the posture of the second surgical instrument, in a case of a first mode, and controls the motion of the robot arm in accordance with a manipulation including contact to the robot arm, in a case of a second mode.

Abstract: A surgery supporting apparatus capable of performing a manipulation using a surgical instrument to be inserted into a body cavity, comprises a measurement device configured to measure an insertion depth and an insertion angle, with respect to the body cavity, of a shaft of the surgical instrument inserted into the body cavity, as input of the manipulation, wherein the measurement device measures the insertion depth by measuring a sound wave propagating in a space between a transmitter attached to one of the surgical instrument and a position within a predetermined range from a position of insertion to the body cavity, and a receiver attached to the other.

Abstract: A surgery assisting apparatus for controlling a posture of a first surgical tool to be inserted into a body cavity and mechanically driven, by using a second surgical tool to be inserted into the body cavity, comprises: a mode switch configured to switch a first mode and a second mode, the second surgical tool being used to control the first surgical tool in the second mode; one or more sensors configured to measure an angle and depth of insertion of a shaft of the second surgical tool into the body cavity; and at least one memory and at least one processor which function as a computing unit configured to determine a target position of a control point that is a point for specifying the posture of the first surgical tool in order to control the posture of the first surgical tool.

Abstract: A data processing system of the invention comprises a special purpose data processing unit for executing a series of predetermined data processings by a special purpose instruction and a general purpose data processing unit for executing processings designated by general purpose instructions. The special purpose data processing unit has a dedicated circuit portion specialized in specific data processings and a sequence control portion that supplies the dedicated circuit portion with control signals to control the dedicated circuit portion in accordance with a predetermined processing procedure. In addition, the general purpose data processing unit can control the dedicated circuit portion in accordance with a procedure different from the processing procedure preset in the sequence control portion. Thus, it is possible to provide the data processing system that can flexibly deal with even such alterations as have an influence on the specification of the special purpose data processing unit.

Abstract: A data processing system is provided that includes a special purpose data processing unit (VU) specialized in a specific data processing according to a special purpose instruction, and a general purpose data processing unit (PU) capable of designating processes by general purpose instructions, and an instruction issue unit for supplying signals corresponding to the special purpose instruction and the general purpose instructions to the PU and the VU respectively, the instruction issue unit being an application-specific unit. By replacing the instruction issue unit with a sequencer specialized in the application, a reliable, compact, low-power consumption data processing system is provided in a short period using the resources resulting from optimization with the programmable VUPU processor capable of flexibly dealing with the specification change while maintaining the real-time response.

Abstract: An input analog data is applied to a plurality of neuron units in a time division manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The products of the time division analog input data and the digital weight data are added in an integrator. While the present sum of the products is output, the previous sum of the products is output simultaneously with the present data, thereby providing outputs in a pipe-line manner. When the output of the first neuron is produced, the second neuron in the same layer produces an output such that the output of the first layer is produced on the output analog bus in a time division manner. This analog neuron unit constitutes an intermediate layer and an output layer. One layer of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer, then the neuron system operates as a layered structure.

Abstract: An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors.

Abstract: A learning system in a neuron computer includes a neural network for receiving an analog signal from a first analog bus through an analog input port in a time divisional manner and performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. A control pattern memory stores a pattern of a signal for controlling the neural network. A sequencer produces an address of the control pattern memory and a weight memory. The weight memory stores weight data of the neural network. A digital control unit controls the neural network, control pattern memory, sequencer, and weight memory, and executes a learning algorithm. The learning system further includes an input control unit provided on the input side of the neural network for selecting an input signal for executing the learning algorithm input from the digital control unit or an analog input signal input from the analog input port.

Abstract: An analogue neuron processor (ANP) performs an operation of sum-of-products of a time divisional analog input signal sequentially input from an analog signal bus and weight data and output an analog signal to an analog signal bus through a nonlinear circuit. A layered type or a feedback type neural network is formed of ANPs. The neural network reads necessary control data from a control pattern memory under the control of micro sequencer and reads the necessary weight data from the weight memory thereby realizing a neuron computer. The neuron computer connects a plurality of ANPs by using a single analog bus, thereby greatly decreasing the number of the wires used for the neural network and also decreasing the size of the circuit. A plurality of ANPs in a single layer simultaneously receives analog signal from an analog bus and carries out a parallel operation in the same time period and ANPs in different layers perform a parallel operation in a pipeline manner, thereby increasing a speed of an operation.

Abstract: A semiconductor integrated circuit device includes basic semiconductor elements arranged regularly in lines and rows and located at intersecting points of the lines and rows and wiring conductor layers arranged among the basic semiconductor elements regularly in lines and rows. In this semiconductor integrated circuit device, according to a desired logic operation, wiring conductor layers are cut or contact holes are formed on the wiring conductor layers to form wiring metal layers and connect the basic semiconductor elements to one another, so that an integrated circuit chip capable of performing the desired logic operation is obtained.

Abstract: Disclosed is a semiconductor device having a large number of basic cells, wherein a plurality of basic cells arranged along rows of a semiconductor substrate form a basic cell array and a plurality of the basic cell arrays are arranged along columns of the substrate, and further including spaces formed between each adjoining column. Each basic cell is comprised of first and second P-channel MIS transistors and first and second N-channel MIS transistors. The gates of both the first P-channel and the first N-channel MIS transistors form a first single common gate, and the gates of both the second P-channel and the second N-channel MIS transistors form a second single common gate. The sources or the drains of both the first P-channel and the second P-channel MIS transistors form a first single common source or drain, and the sources or the drains of both the first N-channel and the second N-channel MIS transistors form a second single common source or drain.