Abstract: An integrated circuit includes a plurality of signal inputs, a receiver, calibration circuitry, and input switch circuitry. The receiver includes differential input terminals. The calibration circuitry is configured to calibrate an input offset between the differential input terminals of the receiver in response to the integrated circuit being placed in a calibration mode. The input switch circuitry is configured to switch electrical connections between the plurality of signal inputs and the differential input terminals of the receiver in response to the integrated circuit being placed in a mode different from the calibration mode. The input switch circuitry is further configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver in response to the integrated circuit being placed in the calibration mode.

Abstract: An integrated circuit includes a plurality of signal inputs, a receiver, calibration circuitry, and input switch circuitry. The receiver includes differential input terminals. The calibration circuitry is configured to calibrate an input offset between the differential input terminals of the receiver in response to the integrated circuit being placed in a calibration mode. The input switch circuitry is configured to switch electrical connections between the plurality of signal inputs and the differential input terminals of the receiver in response to the integrated circuit being placed in a mode different from the calibration mode. The input switch circuitry is further configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver in response to the integrated circuit being placed in the calibration mode.

Abstract: A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

Abstract: A data transmission system for a display device, the data transmission system comprising: an encoder having at least one translation table, encoding m bits of a data into n bits of a data on the basis of the translation table; a parallel-to-serial converter; a clock recovery circuit for recovering a clock from the data encoded and serialized; a serial-to-parallel converter for decoding the n bits of the encoded data to the m bits of the data; and an output driver for outputting a gray scale voltage, wherein an amplitude of the gray scale voltage is determined according to a value of the m bit of the data, and, wherein in the translation table, a larger the amplitude of the gray scale voltage of a bit pattern in 2 m pieces of bit patterns of the m bits of the data, a larger the data change index of the bit pattern.

Abstract: A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.

Abstract: A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

Abstract: A data transmission system for a display device, the data transmission system comprising: an encoder having at least one translation table, encoding m bits of a data into n bits of a data on the basis of the translation table; a parallel-to-serial converter; a clock recovery circuit for recovering a clock from the data encoded and serialized; a serial-to-parallel converter for decoding the n bits of the encoded data to the m bits of the data; and an output driver for outputting a gray scale voltage, wherein an amplitude of the gray scale voltage is determined according to a value of the m bit of the data, and, wherein in the translation table, a larger the amplitude of the gray scale voltage of a bit pattern in 2m pieces of bit patterns of the m bits of the data, a larger the data change index of the bit pattern.

Abstract: A display device includes an encoder having at least one translation table, and encoding m (m is a natural number) bits of a data to n (n is a natural number and n>m) bits of a data on a basis of the at least one translation table; a clock recovery circuit configured to recover a clock from the data encoded by the encoder; a decoder configured to decode the n bits of the encoded data to the m bits of the data in accordance with the clock recovered by the clock recovery circuit; an output driver configured to output a voltage in accordance with the data decoded by the decoder; and a display element having a pixel applied with the voltage.

Abstract: A display control circuit of a display performs generation of overdrive processed data and detection of a proper direction of overdriving from current frame uncompressed compressed data obtained by performing compression processing and uncompression processing on compressed data corresponding to image data of a current frame, and previous frame uncompressed compressed data obtained by performing the compression processing and the uncompression processing on image data of a previous frame, and generates post-correction overdrive processed data by correcting the overdrive processed data according to the detected proper direction. The display control circuit transmits post-correction compressed data obtained by compressing the post-correction overdrive processed data to a driver as transfer compressed data.

Abstract: A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.

Abstract: A display control circuit of a display performs generation of overdrive processed data and detection of a proper direction of overdriving from current frame uncompressed compressed data obtained by performing compression processing and uncompression processing on compressed data corresponding to image data of a current frame, and previous frame uncompressed compressed data obtained by performing the compression processing and the uncompression processing on image data of a previous frame, and generates post-correction overdrive processed data by correcting the overdrive processed data according to the detected proper direction. The display control circuit transmits post-correction compressed data obtained by compressing the post-correction overdrive processed data to a driver as transfer compressed data.

Abstract: A display control circuit of a display performs generation of overdrive processed data and detection of a proper direction of overdriving from current frame uncompressed compressed data obtained by performing compression processing and uncompression processing on compressed data corresponding to image data of a current frame, and previous frame uncompressed compressed data obtained by performing the compression processing and the uncompression processing on image data of a previous frame, and generates post-correction overdrive processed data by correcting the overdrive processed data according to the detected proper direction. The display control circuit transmits post-correction compressed data obtained by compressing the post-correction overdrive processed data to a driver as transfer compressed data.

Abstract: A display device includes an encoder having at least one translation table, and encoding m (m is a natural number) bits of a data to n (n is a natural number and n>m) bits of a data on a basis of the at least one translation table; a clock recovery circuit configured to recover a clock from the data encoded by the encoder; a decoder configured to decode the n bits of the encoded data to the m bits of the data in accordance with the clock recovered by the clock recovery circuit; an output driver configured to output a voltage in accordance with the data decoded by the decoder; and a display element having a pixel applied with the voltage.

Abstract: According to one aspect of the present invention, there is provided a driver of a display unit including a latch circuit holding gradation information, a D/A converter outputting analog signal based on the gradation information held by the latch circuit, a test circuit provided between the latch circuit and the D/A converter, the test circuit inputting or outputting test signal regarding the latch circuit, a switch connecting voltage output of the D/A converter and a driver output terminal in normal operation, and a test switch connecting the test circuit and the driver output terminal in test operation and disconnecting the test circuit and the driver output terminal in normal operation.

Abstract: A data transmission system for a display device, which is an mBnB encoding system encoding a signal of m (m is a natural number) bits into a signal of n (n is a natural number and n>m) bits on the basis of a certain translation table to be transmitted thereafter, the system including: an output driver of outputting a gray scale voltage in accordance with the data decoded at a receiver side, in which in the translation table, a bit pattern with a larger data change index from among 2n pieces of bit patterns of the n bits of the data is assigned to a bit pattern with a larger amplitude of the gray scale voltage from among 2m pieces of bit patterns of the m bits of the data.

Abstract: A display panel driver includes a color reducing circuit and a driving section. The driving section is configured to drive a first pixel and a second pixel. If a second input image data and a third input image data corresponding to the second pixel are supplied as an image data of a second image display format, then the color reducing circuit generates a third color reduction image data and a fourth color reduction image data. If the first input image data is supplied as the image data of the first image display format, then the first selector selects the third error value, and if the second input image data and the third input image data are supplied as the image data of the second image display format, then the first selector selects the second error value.

Abstract: A liquid crystal display device includes a timing controller, a liquid crystal display panel, multiple data drivers, and gate drivers. The timing controller supplies control data to specified drivers among the data drivers. The specified drivers generate gate driver control signals to control gate drivers in response to the control data, and supply gate driver control signals to the gate drivers.

Abstract: A display panel driver includes a color reducing circuit and a driving section. The driving section is configured to drive a first pixel and a second pixel. If a second input image data and a third input image data corresponding to the second pixel are supplied as an image data of a second image display format, then the color reducing circuit generates a third color reduction image data and a fourth color reduction image data. If the first input image data is supplied as the image data of the first image display format, then the first selector selects the third error value, and if the second input image data and the third input image data are supplied as the image data of the second image display format, then the first selector selects the second error value.

Abstract: A display apparatus includes a display panel; and a display panel driver configured to drive signal lines of the display panel. The display panel driver includes: a color reducing circuit configured to be possible to generate a first color reduction image data from a first input image data by executing an error diffusion process by using a first error value, and to generate a second color reduction image data from the first input image data by executing the error diffusion process by using a second error value which is different from the first error value; and a driving section configured to drive a first pixel positioned on a horizontal line of the display panel in response to the first color reduction image data, and drive a second pixel positioned on the horizontal line and adjacent to a the first pixel in a horizontal direction, in response to the second color reduction image data.

Abstract: A display control circuit of a display performs generation of overdrive processed data and detection of a proper direction of overdriving from current frame uncompressed compressed data obtained by performing compression processing and uncompression processing on compressed data corresponding to image data of a current frame, and previous frame uncompressed compressed data obtained by performing the compression processing and the uncompression processing on image data of a previous frame, and generates post-correction overdrive processed data by correcting the overdrive processed data according to the detected proper direction. The display control circuit transmits post-correction compressed data obtained by compressing the post-correction overdrive processed data to a driver as transfer compressed data.