Patents by Inventor Yoshihiko Ikemoto
Yoshihiko Ikemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11121094Abstract: A semiconductor device includes a lead frame, an electronic device, a package body, and a first shield plate. The lead frame includes a die mount structure, signal leads, a first shield lead, a second shield lead, and a first shield mount that spans the first and second shield leads. The electronic device can be mounted to the die mount structure and can be coupled to the signal leads. The package body encapsulates the electronic device and the lead frame such that (i) each of the first shield lead, the second shield lead, and the signal leads includes an external portion that extends beyond the exterior surface of the package body, and (ii) the first shield mount extends beyond the exterior surface of the package body. The first shield plate can be coupled to the first shield mount.Type: GrantFiled: June 20, 2019Date of Patent: September 14, 2021Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Yoshio Matsuda, Kenji Nishikawa, Seiichiro Sato, Yoshihiko Ikemoto
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Publication number: 20200402919Abstract: A semiconductor device includes a lead frame, an electronic device, a package body, and a first shield plate. The lead frame includes a die mount structure, signal leads, a first shield lead, a second shield lead, and a first shield mount that spans the first and second shield leads. The electronic device can be mounted to the die mount structure and can be coupled to the signal leads. The package body encapsulates the electronic device and the lead frame such that (i) each of the first shield lead, the second shield lead, and the signal leads includes an external portion that extends beyond the exterior surface of the package body, and (ii) the first shield mount extends beyond the exterior surface of the package body. The first shield plate can be coupled to the first shield mount.Type: ApplicationFiled: June 20, 2019Publication date: December 24, 2020Applicant: J-Devices CorporationInventors: Yoshio Matsuda, Kenji Nishikawa, Seiichiro Sato, Yoshihiko Ikemoto
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Patent number: 9685376Abstract: A semiconductor device including: a support plate 1; a semiconductor chip 2 mounted on one principal surface of the support plate 1 via an adhesive layer, with the element circuit surface of the chip being directed upward; an insulation material layer 4 that seals the semiconductor chip 2 and the periphery of the semiconductor chip; openings formed on an electrode arranged on the element circuit surface of the semiconductor chip 2 in the insulation material layer 4; conductive portions 6 formed in the openings so as to be connected to the electrode of the semiconductor chip; a wiring layer 5 formed on the insulation material layer 4 so as to be connected to the conductive portions 6 and partially extending to the peripheral region of the semiconductor chip 2; and external electrodes 7 formed on the wiring layer 5.Type: GrantFiled: July 16, 2015Date of Patent: June 20, 2017Assignee: J-DEVICES CORPORATIONInventors: Yoshihiko Ikemoto, Hiroshi Inoue, Kiminori Ishido, Hiroaki Matsubara, Yukari Imaizumi
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Patent number: 9627289Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.Type: GrantFiled: December 9, 2015Date of Patent: April 18, 2017Assignee: J-DEVICES CORPORATIONInventors: Yoshihiko Ikemoto, Shigenori Sawachi, Fumihiko Taniguchi, Akio Katsumata
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Publication number: 20160181194Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.Type: ApplicationFiled: December 9, 2015Publication date: June 23, 2016Inventors: Yoshihiko IKEMOTO, Shigenori SAWACHI, Fumihiko TANIGUCHI, Akio KATSUMATA
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Publication number: 20160027695Abstract: The invention provides a semiconductor device low in height and having low heat resistance, and a method of manufacturing the semiconductor device.Type: ApplicationFiled: July 16, 2015Publication date: January 28, 2016Inventors: Yoshihiko IKEMOTO, Hiroshi INOUE, Kiminori ISHIDO, Hiroaki MATSUBARA, Yukari IMAIZUMI
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Patent number: 8811028Abstract: A semiconductor device for mounting on a wiring board includes: a container for containing a semiconductor chip; and a plurality of leads, each of the plurality of leads includes a mount connection portion at one end for the semiconductor device to be connected to the wiring board, wherein the plurality of leads includes first leads and second leads, a signal transmission rate of the first leads is higher than that of the second leads, and the mount connection portion of each of the first leads is smaller than that of each of the second leads.Type: GrantFiled: December 21, 2010Date of Patent: August 19, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Yoshihiko Ikemoto
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Patent number: 8659120Abstract: There is provided a semiconductor device substrate including: a multi-layer wiring layer; a first capacitor pad which is provided on an uppermost layer of the multi-layer wiring layer, and which includes a first power supply pad connected to a power supply layer of the multi-layer wiring layer through a first via and a first ground pad connected to a ground layer of the multi-layer wiring layer through a second via; and a second capacitor pad which is provided on the uppermost layer of the multi-layer wiring layer, and which includes a second power supply pad connected to the first power supply pad through a first wire and a second ground pad connected to the first ground pad through a second wire.Type: GrantFiled: June 30, 2011Date of Patent: February 25, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Yoshihiko Ikemoto, Atsushi Kikuchi
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Publication number: 20120098091Abstract: There is provided a semiconductor device substrate including: a multi-layer wiring layer; a first capacitor pad which is provided on an uppermost layer of the multi-layer wiring layer, and which includes a first power supply pad connected to a power supply layer of the multi-layer wiring layer through a first via and a first ground pad connected to a ground layer of the multi-layer wiring layer through a second via; and a second capacitor pad which is provided on the uppermost layer of the multi-layer wiring layer, and which includes a second power supply pad connected to the first power supply pad through a first wire and a second ground pad connected to the first ground pad through a second wire.Type: ApplicationFiled: June 30, 2011Publication date: April 26, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yoshihiko Ikemoto, Atsushi Kikuchi
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Publication number: 20110157852Abstract: A semiconductor device for mounting on a wiring board includes: a container for containing a semiconductor chip; and a plurality of leads, each of the plurality of leads includes a mount connection portion at one end for the semiconductor device to be connected to the wiring board, wherein the plurality of leads includes first leads and second leads, a signal transmission rate of the first leads is higher than that of the second leads, and the mount connection portion of each of the first leads is smaller than that of each of the second leads.Type: ApplicationFiled: December 21, 2010Publication date: June 30, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Yoshihiko Ikemoto
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Patent number: 7309917Abstract: Preparing a bottom grounding layer eliminates grounding pins, thereby the number of signal pins can be increased in a multilayer board that includes a grounding layer, a signal layer, a power supply layer, a grounding via, a signal via, a power supply via and the like in the insulation material of the multilayer board, the bottom grounding layer being electrically connected to the grounding layer.Type: GrantFiled: March 3, 2006Date of Patent: December 18, 2007Assignee: Fujitsu LimitedInventors: Yoshiyuki Kimura, Atsushi Kikuchi, Yoshihiko Ikemoto
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Patent number: 7030480Abstract: Preparing a bottom grounding layer eliminates grounding pins, thereby the number of signal pins can be increased in a multilayer board that includes a grounding layer, a signal layer, a power supply layer, a grounding via, a signal via, a power supply via and the like in the insulation material of the multilayer board, the bottom grounding layer being electrically connected to the grounding layer.Type: GrantFiled: January 31, 2003Date of Patent: April 18, 2006Assignee: Fujitsu LimitedInventors: Yoshiyuki Kimura, Atsushi Kikuchi, Yoshihiko Ikemoto
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Patent number: 6888517Abstract: A video display driver circuit adapted to receive and monitor an input video signal, which is associated with information or an image that is subsequently displayed on a display. The video display driver circuit includes circuitry for detecting movement of the information or image displayed on the display and circuitry for adjusting a vertical synchronization frequency associated with the display to enable the moving information or image to be smoothly reproduced in a number of locations on the display.Type: GrantFiled: May 22, 2001Date of Patent: May 3, 2005Assignee: Pioneer Plasma Display CorporationInventor: Yoshihiko Ikemoto
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Patent number: 6796024Abstract: According to the method of producing a semiconductor device, the substrate is provided with an opening formed at a substantially central position, interconnections and joining parts. The heat spreading plate has a fixed portion fixed to the substrate, a stage portion caved with respect to the fixed potion and connecting portions connecting the fixed portion and the stage portion. The heat spreading plate is fixed by positioning the stage portion at a position opposing the opening, then the heat spreading plate is welded to the substrate and the semiconductor chip is mounted on the stage portion through the opening. Then the semiconductor chip and interconnections formed on the substrate are electrically connected and sealing resin is formed on both sides of the heat spreading plate such that at least the semiconductor chip is sealed.Type: GrantFiled: March 20, 2003Date of Patent: September 28, 2004Assignee: Fujitsu LimitedInventors: Yoshitsugu Katoh, Mitsuo Abe, Yoshihiko Ikemoto, Sumikazu Hosoyamada
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Publication number: 20040041277Abstract: Preparing a bottom grounding layer eliminates grounding pins, thereby the number of signal pins can be increased in a multilayer board that includes a grounding layer, a signal layer, a power supply layer, a grounding via, a signal via, a power supply via and the like in the insulation material of the multilayer board, the bottom grounding layer being electrically connected to the grounding layer.Type: ApplicationFiled: January 31, 2003Publication date: March 4, 2004Applicant: FUJITSU LIMITEDInventors: Yoshiyuki Kimura, Atsushi Kikuchi, Yoshihiko Ikemoto
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Publication number: 20030161112Abstract: A semiconductor device includes a semiconductor chip, a substrate electrically connected to the semiconductor chip and heat spreading plate thermally connected to the semiconductor chip. The substrate is provided with external connection terminals on a first surface and electrically connects the semiconductor chip and the external connection terminals. The substrate is provided with joining parts made of metal on a second surface. The heat spreading plate and the substrate are joined together by welding the joining parts and the heat spreading plate.Type: ApplicationFiled: March 20, 2003Publication date: August 28, 2003Applicant: FUJITSU LIMITEDInventors: Yoshitsugu Katoh, Mitsuo Abe, Yoshihiko Ikemoto, Sumikazu Hosoyamada
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Patent number: 6573600Abstract: A multilayer wiring substrate includes differential signal wires placed within a first insulating layer between a first power-supply plane and a first ground plane; and general signal wires placed within a second insulating layer between a second power-supply plane and a second ground plane. In the multilayer wiring substrate, the differential signal wires are placed in a different plane from a plane having each of the general signal wires so that the different plane includes a first area having the differential signal wires, and a second area having one of the second power-supply plane and the second ground plane. The general signal wires are placed in a vertical direction of the second area in a laminated state so that each of the general signal wires is placed between the second power-supply plane and the second ground plane.Type: GrantFiled: March 27, 2001Date of Patent: June 3, 2003Assignee: Fujitsu LimitedInventors: Atsushi Kikuchi, Makoto Iijima, Yoshihiko Ikemoto, Muneharu Morioka, Yoshiyuki Kimura
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Patent number: 6559536Abstract: A semiconductor device includes a semiconductor chip, a substrate electrically connected to the semiconductor chip and heat spreading plate thermally connected to the semiconductor chip. The substrate is provided with external connection terminals on a first surface and electrically connects the semiconductor chip and the external connection terminals. The substrate is provided with joining , parts made of metal on a second surface. The heat spreading plate and the substrate are joined together by welding the joining parts and the heat spreading plate.Type: GrantFiled: July 7, 2000Date of Patent: May 6, 2003Assignee: Fujitsu LimitedInventors: Yoshitsugu Katoh, Mitsuo Abe, Yoshihiko Ikemoto, Sumikazu Hosoyamada
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Patent number: 6424032Abstract: In a semiconductor device, an influence of the simultaneous switching noise is reduced by increasing the decoupling capacity between a ground ring and a power supply ring. A semiconductor element having a plurality of electrode pads is mounted on a redistribution substrate. The power supply ring and the ground ring are formed on the redistribution substrate in a surrounding area of the semiconductor element. One of the ground ring and the power supply ring has a plurality of convex portions protruding toward the other of the ground ring and the power supply ring. The other of the ground ring and the power supply ring has a plurality of concave portions each of which receives the corresponding one of the convex portions with a predetermined distance therebetween.Type: GrantFiled: August 23, 2000Date of Patent: July 23, 2002Assignee: Fujitsu LimitedInventors: Yoshihiko Ikemoto, Mitsuo Abe, Yoshitsugu Katoh, Sumikazu Hosoyamada
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Publication number: 20020060366Abstract: A multilayer wiring substrate comprises differential signal wires placed within a first insulating layer between a first power-supply plane and a first ground plane; and general signal wires placed within a second insulating layer between a second power-supply plane and a second ground plane. In the multilayer wiring substrate, the differential signal wires are placed in a different plane from a plane having each of the general signal wires so that the different plane includes a first area having the differential signal wires, and a second area having one of the second power-supply plane and the second ground plane. The general signal wires are placed in a vertical direction of the second area in a laminated state so that each of the general signal wires is placed between the second power-supply plane and the second ground plane.Type: ApplicationFiled: March 27, 2001Publication date: May 23, 2002Inventors: Atsushi Kikuchi, Makoto Iijima, Yoshihiko Ikemoto, Muneharu Morioka, Yoshiyuki Kimura