Patents by Inventor Yoshihiko Imamura

Yoshihiko Imamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12143200
    Abstract: A terminal apparatus includes circuitry and a transmitter. The circuitry, in operation, generates a reference signal using a cyclic shift value and an orthogonal sequence, which are associated with each other. The orthogonal sequence is one of two orthogonal sequences corresponding to a first orthogonal sequence [1, 1] and a second orthogonal sequence [1, ?1]. The cyclic shift value is one of 12 cyclic shift values ranging from 0 to 11. The transmitter, in operation, transmits the reference signal multiplexed with a data signal. Two of the cyclic shift values having a difference of 6 are respectively associated with the two orthogonal sequences.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: November 12, 2024
    Assignee: Sun Patent Trust
    Inventors: Yoshihiko Ogawa, Akihiko Nishio, Takashi Iwai, Seigo Nakao, Daichi Imamura, Atsushi Sumasu
  • Publication number: 20240367103
    Abstract: An ethylene oxide gas removal method is a method for removing ethylene oxide gas emitted into a predetermined partition space). The method includes: a first step of suctioning EO-containing air that contains ethylene oxide emitted into the partition space and supplying the EO-containing air to a concentration device; a second step of removing a water content from the suctioned EO-containing air, and thereafter adsorbing and concentrating ethylene oxide by an adsorbing material, in the concentration device; a third step of desorbing the concentrated ethylene oxide from the adsorbing material and sending the ethylene oxide to a removal device; and a fourth step of decomposing and removing ethylene oxide gas by the removal device.
    Type: Application
    Filed: September 15, 2021
    Publication date: November 7, 2024
    Inventors: Atsushi MORIHARA, Yoshihiko KATO, Hiroki KUZUOKA, Hiroshi IMAMURA, Kazuya HAYASHI
  • Patent number: 12132566
    Abstract: Provided is a sequence allocation method capable of reducing inter-cell interference of a reference signal when a ZC sequence is used as the reference signal in a mobile communication system. In the sequence allocation method, R×M sequences specified by a ZC sequence number r (r=1 to R) and a cyclic shift sequence number m (m=1 to M) are divided into a plurality of sequence groups X (X=1 to R) in accordance with the transmission band width of the reference signal, so that the ZC sequence is allocated to each cell in each sequence group unit. When it is assumed that R=9 and M=6, the number of sequences is 54. Each of the sequence groups is formed by two sequences. Accordingly, the number of sequence groups is 27. The 27 types of sequence groups are allocated to each cell.
    Type: Grant
    Filed: August 18, 2023
    Date of Patent: October 29, 2024
    Assignee: Panasonic Holdings Corporation
    Inventors: Yoshihiko Ogawa, Daichi Imamura, Sadaki Futagi, Tomofumi Takata
  • Patent number: 12108373
    Abstract: It is an object to provide a sequence allocating method that, while maintaining the number of Zadoff-Chu sequences to compose a sequence group, is configured to make it possible to reduce correlations between different sequential groups. This method comprises the steps of setting a standard sequence with a standard sequence length and a standard sequence number in a step, setting a threshold value in accordance with an RB number in a step, setting a sequence length corresponding to RB number in a step, judging whether ¦r/N?rb/Nb¦=Xth(m) is satisfied in a step, including a plurality of Zadoff-Chu sequences with a sequence number and a sequence length in a sequence group in a step if the judgment is positive, and allocating the sequence group to the same cell in a step.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: October 1, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Takashi Iwai, Daichi Imamura, Tomofumi Takata, Yoshihiko Ogawa
  • Publication number: 20240314701
    Abstract: Disclosed is a wireless communication device that can suppress an increase in power consumption of a terminal while preventing the degradation of SINR measurement precision resulting from TPC errors in a base station. A terminal controls the transmission power of a second signal by adding an offset to the transmission power of a first signal; an offset-setting unit sets an offset correction value in response to a transmission time gap between a third signal transmitted the previous time and the second signal transmitted this time; and a transmission power control unit controls the transmission power of the second signal using the correction value.
    Type: Application
    Filed: May 22, 2024
    Publication date: September 19, 2024
    Inventors: Takashi IWAI, Daichi IMAMURA, Akihiko NISHIO, Yoshihiko OGAWA, Shinsuke TAKAOKA
  • Publication number: 20240259156
    Abstract: Disclosed are a wireless transmitter and a reference signal transmission method that improve channel estimation accuracy. In a terminal, which transmits a reference signal using n (n is a non-negative integer 2 or greater) band blocks (which correspond to clusters here), which are disposed with spaces therebetween in a frequency direction, a reference signal controller switches the reference signal formation method of a reference signal generator between a first formation method and a second formation method based on the number (n) of band blocks. In addition, a threshold value setting unit adjusts a switching threshold value based on the frequency spacing between band blocks. Thus, the reference signal formation method can be selected with good accuracy and, as a result, channel estimation accuracy is further improved.
    Type: Application
    Filed: April 9, 2024
    Publication date: August 1, 2024
    Inventors: Takashi IWAI, Sadaki FUTAGI, Tomohumi TAKATA, Daichi IMAMURA, Yoshihiko OGAWA
  • Patent number: 7032099
    Abstract: A parallel processor capable of establishing synchronization among programs executed in parallel, wherein a processor element suspends its processing and enters a waiting state when a wait instruction “sleep” is executed in a user program Prg_d and resumes the processing by releasing the above waiting state based on execution of a wait release instruction “cont(Prg_d)” by another processor element and wherein the latter processor element executes a next instruction without suspending its processing after executing the wait release instruction “cont(Prg_d)”.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: April 18, 2006
    Assignee: Sony Corporation
    Inventor: Yoshihiko Imamura
  • Patent number: 6725355
    Abstract: A microprocessor having an internal memory for storing data to be process, a data pointer register for storing an address on the internal memory, a decoder 36 for decoding an instruction, a general-purpose register module 11 including data registers r0 and r1 for storing data read from an address on the internal memory stored in the data pointer register in accordance with a request to read data stored in the internal memory, and an ALU 13 for performing processing using data stored in the general-purpose register module 11 based on the result of decoding by the decoder 36 and writing the result of processing in the general-purpose register module 11.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: April 20, 2004
    Assignee: Sony Corporation
    Inventor: Yoshihiko Imamura
  • Patent number: 6581089
    Abstract: A parallel processing apparatus capable of flexibly solving at a high speed the problem of synchronization wait when a plurality of tasks are generated, wherein a processor element PE12 specifies pipe counters and calls up a plurality of tasks with respect to processor elements PE13 to PE15 and waits for synchronization according to need by a synchronization wait command, an arbiter 56 increases a count value of a corresponding pipe counter when a task is called up and decreases the count value of the corresponding pipe counter when the task is ended, and the processor element PE12 compares the count value contained in the synchronization wait command and the count value of the corresponding pipe counter of the arbiter 56 when executing the synchronization wait command, releases the synchronization wait when they coincide, and enters the synchronization wait when they do not coincide.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: June 17, 2003
    Assignee: Sony Corporation
    Inventor: Yoshihiko Imamura
  • Patent number: 6381686
    Abstract: A parallel processor capable of exhibiting a high processing performance, which when receiving as input access requests generating page faults to sub-banks from a plurality of processor elements connected to a common bus and another access request is input while data is being transferred between sub banks and an external memory via an external access bus in response to the input access requests, a shared memory stores the other access request in a request queue and makes a control circuit execute the stored access request when the stored access request does not generate a page fault.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: April 30, 2002
    Assignee: Sony Corporation
    Inventor: Yoshihiko Imamura
  • Patent number: 6349370
    Abstract: A parallel processor having a high processing performance, where, before the end of a page transfer with an outside memory via an external access bus by a first access request accompanied with a page fault from one processor element to a shared memory, a second access request is generated having a page fault from another processor element to the shared memory, the sub-page requested by the first and second access requests is transferred from the outside memory to the shared memory first, and other sub-pages in the page to which the requested sub-page belongs are transferred from the outside memory to the shared memory.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: February 19, 2002
    Assignee: Sony Corporation
    Inventor: Yoshihiko Imamura
  • Patent number: 5394845
    Abstract: An engine intake system includes a primary port for introducing intake gas throughout an entire engine operating condition. A secondary port is provided with a gate valve which is opened in a high engine load condition for introducing the intake gas. A ratio of a tumble flow to a swirl flow is gradually increased as the gate valve is operated from an entirely closed condition to a fully open condition. According to this invention, ignition and combustion characteristics can be improved.
    Type: Grant
    Filed: October 15, 1992
    Date of Patent: March 7, 1995
    Assignee: Mazda Motor Corporation
    Inventors: Yoshihisa Noh, Yoshihiko Imamura, Fumihiko Saito, Kazuhiko Hashimoto, Masanori Misumi
  • Patent number: 5335634
    Abstract: A combustion chamber for an engine is provided between a cylinder bore formed in a cylinder block, a generally conically-shaped wall formed in an under wall of a cylinder head, and a piston in the cylinder bore. The combustion chamber has a structure into which an intake port opens so as to introduce an intake air flow closer to a marginal portion than a central portion of the combustion chamber, thereby generating a swirl flow of intake air in the combustion chamber. The combustion chamber also includes a curved air flow guide wall formed in the generally conically-shaped wall which extends from near the intake port so as to approach the cylinder bore surface gradually, thereby generating what is termed a squish flow of intake air.
    Type: Grant
    Filed: May 14, 1992
    Date of Patent: August 9, 1994
    Assignee: Mazda Motor Corporation
    Inventors: Kazuhiko Hashimoto, Yoshihiko Imamura, Toshihide Yamamoto, Yoshihisa Noh
  • Patent number: 4723973
    Abstract: An exhaust-gas purifying apparatus according to the present invention comprises an exhaust-gas filter for trapping particulates in exhaust gas from an engine, and a heating device located on the upper-course side of the filter, with respect to the flowing direction of the exhaust gas, the heating device including one or more conductive-ceramic heater elements, capable of heating and burning the particulates caught by the filter, and a heater case for holding the heater elements in position, so that the caught particulates are heated and burned by the heater elements when the flow resistance of the exhaust gas, flowing through the filter, is increased by the caught particulates, whereby the flow resistance is reduced. The heater element includes a fixed electrode portion, immovably fixed to the heater case, and a slidable electrode portion held slidably.
    Type: Grant
    Filed: September 26, 1986
    Date of Patent: February 9, 1988
    Assignees: Nippondenso Co., Ltd., Toyota Jidosha Kabushiki Kaisha
    Inventors: Kazuo Oyobe, Hiroki Hoshizaki, Terutaka Kageyama, Hirofumi Suzuki, Yoshihiko Imamura, Kiyoshi Kobashi, Kenichiro Takama, Shinichi Takeshima
  • Patent number: 4723069
    Abstract: A ceramic heater for regenerating a fine particle collecting filter which is exposed to exhaust gases at elevated temperatures. This ceramic heater comprises two electrode potions, a heat generation portion connected to the two electrode portions and a holding projection portion of a ceramic heater connected to the side of the heat generating portion. The two electrode portions, the heat generating portion and the holding projection portion are formed integrally.
    Type: Grant
    Filed: September 16, 1986
    Date of Patent: February 2, 1988
    Assignees: Toyota Jidosha Kabushiki Kaisha, Nippondenso Co., Ltd.
    Inventors: Hiroki Hoshizaki, Kazuo Oyobe, Hirofumi Suzuki, Nobuaki Kawahara, Terutaka Kageyama, Hitoshi Niwa, Shinichi Takeshima, Yoshihiko Imamura, Kiyoshi Kobashi, Kenichiro Takama