Abstract: Provided is a radio communication device which can prevent interference between SRS and PUCCH when the PUCCH transmission bandwidth fluctuates and suppress degradation of CQI estimation accuracy by the band where no SRS is transmitted. The device includes: an SRS code generation unit (201) which generates an SRS (Sounding Reference Signal) for measuring uplink line data channel quality; an SRS arrangement unit (202) which frequency-multiplexes the SRS on the SR transmission band and arranges it; and an SRS arrangement control unit (208) which controls SRS frequency multiplex so as to be uniform in frequency without modifying the bandwidth of one SRS multiplex unit in accordance with the fluctuation of the reference signal transmission bandwidth according to the SRS arrangement information transmitted from the base station and furthermore controls the transmission interval of the frequency-multiplexed SRS.

Abstract: A radio communication apparatus is provided, which includes a receiver and a controller. The receiver, in operation, receives a first power headroom (PHR), which is obtained by subtracting a transmit power for a data channel from a maximum transmit power at a mobile station and which is transmitted from the mobile station, and receives a second PHR, which is obtained by subtracting the transmit power for the data channel and a transmit power for a control channel from the maximum transmit power at the mobile station and which is transmitted from the mobile station. The controller, in operation, selectively sets a simultaneous transmission of the data channel and the control channel in different frequency bands to be performed by the mobile station. When the data channel and the control channel are simultaneously transmitted in different frequency bands from the mobile station, the second PHR is obtained and transmitted from the mobile station.

Abstract: Disclosed are a wireless transmitter and a reference signal transmission method that improve channel estimation accuracy. In a terminal, which transmits a reference signal using n (n is a non-negative integer 2 or greater) band blocks (which correspond to clusters here), which are disposed with spaces therebetween in a frequency direction, a reference signal controller switches the reference signal formation method of a reference signal generator between a first formation method and a second formation method based on the number (n) of band blocks. In addition, a threshold value setting unit adjusts a switching threshold value based on the frequency spacing between band blocks. Thus, the reference signal formation method can be selected with good accuracy and, as a result, channel estimation accuracy is further improved.

Abstract: An integrated circuit includes circuitry, which, in operation, controls transmitting downlink data to a terminal apparatus; receiving a plurality of transport blocks which are transmitted in a same time period using a same frequency band in a spatial multiplexing scheme, wherein a same acknowledgement information (ACK/NACK) relating to an error detection result of the downlink data is scrambled with different scrambling schemes respectively for the plurality of transport blocks and the respectively scrambled ACK/NACK is multiplexed with data on respective ones of the plurality of transport blocks, and channel quality information (CQI) of a downlink channel is multiplexed with the data on only one transport block of the plurality of transport blocks by the terminal apparatus; and extracting the ACK/NACK and the CQI from the received plurality of transport blocks.

Abstract: A terminal apparatus includes circuitry and a transmitter. The circuitry, in operation, generates a reference signal using a cyclic shift value and an orthogonal sequence, which are associated with each other. The orthogonal sequence is one of two orthogonal sequences corresponding to a first orthogonal sequence [1, 1] and a second orthogonal sequence [1, ?1]. The cyclic shift value is one of 12 cyclic shift values ranging from 0 to 11. The transmitter, in operation, transmits the reference signal multiplexed with a data signal. Two of the cyclic shift values having a difference of 6 are respectively associated with the two orthogonal sequences.

Abstract: A parallel processor capable of establishing synchronization among programs executed in parallel, wherein a processor element suspends its processing and enters a waiting state when a wait instruction “sleep” is executed in a user program Prg_d and resumes the processing by releasing the above waiting state based on execution of a wait release instruction “cont(Prg_d)” by another processor element and wherein the latter processor element executes a next instruction without suspending its processing after executing the wait release instruction “cont(Prg_d)”.

Abstract: A microprocessor having an internal memory for storing data to be process, a data pointer register for storing an address on the internal memory, a decoder 36 for decoding an instruction, a general-purpose register module 11 including data registers r0 and r1 for storing data read from an address on the internal memory stored in the data pointer register in accordance with a request to read data stored in the internal memory, and an ALU 13 for performing processing using data stored in the general-purpose register module 11 based on the result of decoding by the decoder 36 and writing the result of processing in the general-purpose register module 11.

Abstract: A parallel processing apparatus capable of flexibly solving at a high speed the problem of synchronization wait when a plurality of tasks are generated, wherein a processor element PE12 specifies pipe counters and calls up a plurality of tasks with respect to processor elements PE13 to PE15 and waits for synchronization according to need by a synchronization wait command, an arbiter 56 increases a count value of a corresponding pipe counter when a task is called up and decreases the count value of the corresponding pipe counter when the task is ended, and the processor element PE12 compares the count value contained in the synchronization wait command and the count value of the corresponding pipe counter of the arbiter 56 when executing the synchronization wait command, releases the synchronization wait when they coincide, and enters the synchronization wait when they do not coincide.

Abstract: A parallel processor capable of exhibiting a high processing performance, which when receiving as input access requests generating page faults to sub-banks from a plurality of processor elements connected to a common bus and another access request is input while data is being transferred between sub banks and an external memory via an external access bus in response to the input access requests, a shared memory stores the other access request in a request queue and makes a control circuit execute the stored access request when the stored access request does not generate a page fault.

Abstract: A parallel processor having a high processing performance, where, before the end of a page transfer with an outside memory via an external access bus by a first access request accompanied with a page fault from one processor element to a shared memory, a second access request is generated having a page fault from another processor element to the shared memory, the sub-page requested by the first and second access requests is transferred from the outside memory to the shared memory first, and other sub-pages in the page to which the requested sub-page belongs are transferred from the outside memory to the shared memory.

Abstract: An engine intake system includes a primary port for introducing intake gas throughout an entire engine operating condition. A secondary port is provided with a gate valve which is opened in a high engine load condition for introducing the intake gas. A ratio of a tumble flow to a swirl flow is gradually increased as the gate valve is operated from an entirely closed condition to a fully open condition. According to this invention, ignition and combustion characteristics can be improved.

Abstract: A combustion chamber for an engine is provided between a cylinder bore formed in a cylinder block, a generally conically-shaped wall formed in an under wall of a cylinder head, and a piston in the cylinder bore. The combustion chamber has a structure into which an intake port opens so as to introduce an intake air flow closer to a marginal portion than a central portion of the combustion chamber, thereby generating a swirl flow of intake air in the combustion chamber. The combustion chamber also includes a curved air flow guide wall formed in the generally conically-shaped wall which extends from near the intake port so as to approach the cylinder bore surface gradually, thereby generating what is termed a squish flow of intake air.

Abstract: An exhaust-gas purifying apparatus according to the present invention comprises an exhaust-gas filter for trapping particulates in exhaust gas from an engine, and a heating device located on the upper-course side of the filter, with respect to the flowing direction of the exhaust gas, the heating device including one or more conductive-ceramic heater elements, capable of heating and burning the particulates caught by the filter, and a heater case for holding the heater elements in position, so that the caught particulates are heated and burned by the heater elements when the flow resistance of the exhaust gas, flowing through the filter, is increased by the caught particulates, whereby the flow resistance is reduced. The heater element includes a fixed electrode portion, immovably fixed to the heater case, and a slidable electrode portion held slidably.

Abstract: A ceramic heater for regenerating a fine particle collecting filter which is exposed to exhaust gases at elevated temperatures. This ceramic heater comprises two electrode potions, a heat generation portion connected to the two electrode portions and a holding projection portion of a ceramic heater connected to the side of the heat generating portion. The two electrode portions, the heat generating portion and the holding projection portion are formed integrally.