Abstract: A semiconductor device comprises a semiconductor chip mounted within a prepared aperture formed in a flexible film carrier. A conductive lead pattern is formed on the surface of the film carrier and the inner lead ends of the lead pattern project over and into the film aperture in aligned relation with a plurality of bonding pads formed on the active surface of the semiconductor chip. The semiconductor chip, or the semiconductor chip together with inner portions of the conductive lead pattern, are encapsulated with a sealing resin to the film carrier. A spatial interval, A defined by the edge of the carrier aperture and the edge of the outer side periphery of the semiconductor chip to be installed in the device aperture, is set within the range of about 0.4 mm to 0.8 mm. Also, the inner leads are provide with a small extended length, preferably in those portions extending into and over the device aperture.

Abstract: A structure and method are disclosed for tape automated bonding (TAB) assembly processes which provide for reduced manufacturing costs, greater film strength, and greater usable film area so that larger chips can be accommodated on a given size film. Common lines, which prevent the buildup of voltage differences between leads, are cut away before electrical testing by means of a knife that slices away the common line conductors parallel to the film surface rather than punching through the conductive leads attached to the common lines and underlying film. By eliminating the punch-outs more room is made available for large chips, film strength is not reduced because of multiple punch-outs, and manufacturing costs are reduced because product-specific punching tools are no longer required.