Patents by Inventor Yoshihiko Nagahama
Yoshihiko Nagahama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250040287Abstract: A first substrate having a plurality of photoelectric transducers formed on the first substrate, a second substrate having a pixel transistor for each of sets of two or more of the photoelectric transducers as a constituent unit, the pixel transistor being shared by the set and formed on the second substrate, and a second wiring which is connected to a first wiring formed on the second substrate via one contact, and is connected to a plurality of first elements, the first wiring leading to a second element shared by a plurality of first elements among a plurality of elements formed on the first substrate, each of the plurality of first elements being formed for each of the photoelectric transducers are included.Type: ApplicationFiled: October 8, 2024Publication date: January 30, 2025Inventor: Yoshihiko NAGAHAMA
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Patent number: 12148787Abstract: A first substrate having a plurality of photoelectric transducers formed on the first substrate, a second substrate having a pixel transistor for each of sets of two or more of the photoelectric transducers as a constituent unit, the pixel transistor being shared by the set and formed on the second substrate, and a second wiring which is connected to a first wiring formed on the second substrate via one contact, and is connected to a plurality of first elements, the first wiring leading to a second element shared by a plurality of first elements among a plurality of elements formed on the first substrate, each of the plurality of first elements being formed for each of the photoelectric transducers are included.Type: GrantFiled: October 15, 2019Date of Patent: November 19, 2024Assignee: Sony Semiconductor Solutions CorporationInventor: Yoshihiko Nagahama
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Publication number: 20240258358Abstract: An image sensor comprises a first substrate having a first photoelectric transducer and a second photoelectric transducer formed on the first substrate, a first wiring formed on the first substrate and connected to the first photoelectric transducer and the second photoelectric transducer, a second substrate having a pixel transistor formed on the second substrate, the pixel transistor being connected to the first photoelectric transducer and the second photoelectric transducer, a second wiring formed on the second substrate, and a third wiring formed to penetrate the first substrate and the second substrate and connected to the first wiring and the second wiring.Type: ApplicationFiled: April 11, 2024Publication date: August 1, 2024Inventor: Yoshihiko NAGAHAMA
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Publication number: 20220123040Abstract: A semiconductor device according to an embodiment of the present disclosure has a first wiring layer and a first insulating layer stacked therein. The first wiring layer includes a plurality of first wiring lines extending in one direction. The first insulating layer is provided on the first wiring layer. The first insulating layer forms a gap at least partially between the plurality of wiring lines. The first insulating layer has, above the gap, a stack region in which a first insulating film and a second insulating film are stacked. The first insulating film and the second insulating film include materials different from each other.Type: ApplicationFiled: February 21, 2020Publication date: April 21, 2022Inventor: YOSHIHIKO NAGAHAMA
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Publication number: 20210343776Abstract: A first substrate having a plurality of photoelectric transducers formed on the first substrate, a second substrate having a pixel transistor for each of sets of two or more of the photoelectric transducers as a constituent unit, the pixel transistor being shared by the set and formed on the second substrate, and a second wiring which is connected to a first wiring formed on the second substrate via one contact, and is connected to a plurality of first elements, the first wiring leading to a second element shared by a plurality of first elements among a plurality of elements formed on the first substrate, each of the plurality of first elements being formed for each of the photoelectric transducers are included.Type: ApplicationFiled: October 15, 2019Publication date: November 4, 2021Inventor: Yoshihiko NAGAHAMA
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Patent number: 11127773Abstract: Provided is a semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between at least two substrates among the plurality of substrates have an electrode junction structure in which electrodes on the respective bonding surfaces are in direct contact with each other. The electrode junction structure is for electrical connection between the two substrates. In at least one of the two substrates, at least one of the electrode constituting the electrode junction structure or a via for connection of the electrode to a wiring line in the multi-layered wiring layer has a structure in which a protective film for prevention of diffusion of an electrically-conductive material constituting the electrode and the via is inside the electrically-conductive material.Type: GrantFiled: February 15, 2018Date of Patent: September 21, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Yoshihiko Nagahama
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Patent number: 10917546Abstract: An imaging device includes a light shield that has light shielding walls and a plurality of light transmissive parts in a plurality of apertures between the light shielding walls and a light-receiving element layer in which a large number of light-receiving elements that perform photoelectric conversion corresponding to incident light inputted through the light transmissive parts of the light shield are arranged to acquire image information that has passed through optical elements that are different between the adjacent light transmissive parts. Further, the image information that passed through optical elements being different for every one of the light transmissive parts adjacent is acquired, and therefore, the sensor areas of the light receiving element is utilized effectively.Type: GrantFiled: June 6, 2017Date of Patent: February 9, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshihiko Nagahama, Kunihiko Hikichi, Atsushi Yamamoto
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Publication number: 20200035736Abstract: [Object] To enable reliability to be further improved in a semiconductor device. [Solution] Provided is a semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between at least two substrates among the plurality of substrates have an electrode junction structure in which electrodes formed on the respective bonding surfaces are joined in direct contact with each other, the electrode junction structure being a structure for electrical connection between the two substrates.Type: ApplicationFiled: February 15, 2018Publication date: January 30, 2020Inventor: YOSHIHIKO NAGAHAMA
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Patent number: 10438983Abstract: Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.Type: GrantFiled: March 17, 2016Date of Patent: October 8, 2019Assignee: Sony CorporationInventors: Keiji Tatani, Takuji Matsumoto, Yasushi Tateshita, Fumihiko Koga, Takashi Nagano, Takahiro Toyoshima, Tetsuji Yamaguchi, Keiichi Nakazawa, Naoyuki Miyashita, Yoshihiko Nagahama
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Publication number: 20190297234Abstract: [Object] To effectively utilize a sensor area of a light-receiving element. [Solution] An imaging device according to the present disclosure includes: a light shield that has light shielding walls and a plurality of light transmissive parts formed in a plurality of apertures between the light shielding walls; and a light-receiving element layer in which a large number of light-receiving elements that perform photoelectric conversion corresponding to incident light inputted through the light transmissive parts of the light shield are arranged to acquire image information that has passed through optical elements that are different between the adjacent light transmissive parts. According to this configuration, the image information that passed through optical elements being different for every one of the light transmissive parts adjacent is acquired, and therefore, the sensor areas of the light receiving element is utilized effectively.Type: ApplicationFiled: June 6, 2017Publication date: September 26, 2019Inventors: YOSHIHIKO NAGAHAMA, KUNIHIKO HIKICHI, ATSUSHI YAMAMOTO
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Publication number: 20160197109Abstract: Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.Type: ApplicationFiled: March 17, 2016Publication date: July 7, 2016Inventors: Keiji Tatani, Takuji Matsumoto, Yasushi Tateshita, Fumihiko Koga, Takashi Nagano, Takahiro Toyoshima, Tetsuji Yamaguchi, Keiichi Nakazawa, Naoyuki Miyashita, Yoshihiko Nagahama
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Publication number: 20140327052Abstract: Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.Type: ApplicationFiled: April 3, 2014Publication date: November 6, 2014Applicant: Sony CorporationInventors: Keiji Tatani, Takuji Matsumoto, Yasushi Tateshita, Fumihiko Koga, Takashi Nagano, Takahiro Toyoshima, Tetsuji Yamaguchi, Keiichi Nakazawa, Naoyuki Miyashita, Yoshihiko Nagahama
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Patent number: 8728852Abstract: A solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.Type: GrantFiled: July 8, 2011Date of Patent: May 20, 2014Assignee: Sony CorporationInventors: Keiji Tatani, Takuji Matsumoto, Yasushi Tateshita, Fumihiko Koga, Takashi Nagano, Takahiro Toyoshima, Tetsuji Yamaguchi, Keiichi Nakazawa, Naoyuki Miyashita, Yoshihiko Nagahama
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Publication number: 20110269259Abstract: A solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Applicant: SONY CORPORATIONInventors: Keiji Tatani, Takuji Matsumoto, Yasushi Tateshita, Fumihiko Koga, Takashi Nagano, Takahiro Toyoshima, Tetsuji Yamaguchi, Keiichi Nakazawa, Naoyuki Miyashita, Yoshihiko Nagahama
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Patent number: 7977751Abstract: Disclosed herein is an insulated gate field effect transistor including: (A) a source/drain region and a channel formation region; (B) a gate electrode formed above the channel formation region; and (C) a gate insulating film; wherein the gate insulating film is composed of a gate insulating film main body portion formed between the gate electrode and the channel formation region, and a gate insulating film extension portion extending from the insulating film main body portion to a middle of a side surface portion of the gate electrode, and when a height of the gate electrode is HGate and a height of the gate insulating film extension portion is HIns with a surface of the channel formation region as a reference, a relationship of HIns<HGate is fulfilled.Type: GrantFiled: February 5, 2008Date of Patent: July 12, 2011Assignee: Sony CorporationInventors: Kojiro Nagaoka, Yoshihiko Nagahama
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Patent number: 7795688Abstract: A semiconductor device including, on a substrate, a first conduction type MOS transistor having a gate electrode provided in a first trench formed in an insulation film on the substrate, and a second conduction type MOS transistor having a gate electrode provided in a second trench formed in the insulation film, the first conduction type and the second conduction type being opposite types.Type: GrantFiled: June 8, 2006Date of Patent: September 14, 2010Assignee: Sony CorporationInventor: Yoshihiko Nagahama
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Publication number: 20090256226Abstract: Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.Type: ApplicationFiled: April 8, 2009Publication date: October 15, 2009Applicant: Sony CorporationInventors: Keiji Tatani, Takuji Matsumoto, Yasushi Tateshita, Fumihiko Koga, Takashi Nagano, Takahiro Toyoshima, Tetsuji Yamaguchi, Keiichi Nakazawa, Naoyuki Miyashita, Yoshihiko Nagahama
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Publication number: 20080185637Abstract: Disclosed herein is an insulated gate field effect transistor including: (A) a source/drain region and a channel formation region; (B) a gate electrode formed above the channel formation region; and (C) a gate insulating film; wherein the gate insulating film is composed of a gate insulating film main body portion formed between the gate electrode and the channel formation region, and a gate insulating film extension portion extending from the insulating film main body portion to a middle of a side surface portion of the gate electrode, and when a height of the gate electrode is HGate and a height of the gate insulating film extension portion is HIns with a surface of the channel formation region as a reference, a relationship of HIns<HGate is fulfilled.Type: ApplicationFiled: February 5, 2008Publication date: August 7, 2008Applicant: SONY CORPORATIONInventors: Kojiro Nagaoka, Yoshihiko Nagahama
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Publication number: 20060278934Abstract: A semiconductor device including, on a substrate, a first conduction type MOS transistor having a gate electrode provided in a first trench formed in an insulation film on the substrate, and a second conduction type MOS transistor having a gate electrode provided in a second trench formed in the insulation film, the first conduction type and the second conduction type being opposite types.Type: ApplicationFiled: June 8, 2006Publication date: December 14, 2006Inventor: Yoshihiko Nagahama