Patents by Inventor Yoshihiko Okayama

Yoshihiko Okayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10295386
    Abstract: An electromagnetic flow meter includes a measurement tube, an excitation coil, an excitation current supplying unit supplying an excitation current with an excitation frequency fex to the excitation coil, a pair of electrodes disposed inside the measurement tube, a measuring unit measuring a flow based on an emf that arises between the electrodes, a first A/D converting unit that converts the emf to a digital signal, a sampling unit sampling the digital signal, a noise evaluation value calculating unit, based on at least the sample data sampled by the sampling unit, calculating as a noise evaluation value the magnitude of the impact of a noise component owing to adherence of foreign matter to the electrodes upon the measurement of the flow, and an electrode scaling diagnosing unit determining an electrode foreign matter adherence state by comparing the noise evaluation value and a predetermined diagnostic threshold value.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: May 21, 2019
    Assignee: Azbil Corporation
    Inventors: Vince Dooley, Yoshihiko Okayama, Shinsuke Matsunaga, Ichiro Mitsutake
  • Publication number: 20130238259
    Abstract: An electromagnetic flow meter includes a measurement tube, an excitation coil, an excitation current supplying unit supplying an excitation current with an excitation frequency fex to the excitation coil, a pair of electrodes disposed inside the measurement tube, a measuring unit measuring a flow based on an emf that arises between the electrodes, a first A/D converting unit that converts the emf to a digital signal, a sampling unit sampling the digital signal, a noise evaluation value calculating unit, based on at least the sample data sampled by the sampling unit, calculating as a noise evaluation value the magnitude of the impact of a noise component owing to adherence of foreign matter to the electrodes upon the measurement of the flow, and an electrode scaling diagnosing unit determining an electrode foreign matter adherence state by comparing the noise evaluation value and a predetermined diagnostic threshold value.
    Type: Application
    Filed: November 19, 2010
    Publication date: September 12, 2013
    Applicant: AZBIL CORPORATION
    Inventors: Vince Ddoley, Yoshihiko Okayama, Shinsuke Matsunaga, Ichiro Mitsutake
  • Patent number: 4754427
    Abstract: In a programmable controller linking system, a plurality of programmable controllers are connected to one master controller and sequences of the programmable controllers are programmed using addresses representing optional input/output memory areas. Link tables are prepared by automatically allotting input/output memory areas of the programmable controllers, to the inner relays, with respect to addresses of the respective programmable controllers except for the subject programmable controller, the thus prepared link tables are registered in the master controller, and all the link tables are collected from the respective programmable controllers in the master controller at the link starting time to prepare an editorial link table by collecting common portions of the collected link tables.
    Type: Grant
    Filed: January 10, 1986
    Date of Patent: June 28, 1988
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventor: Yoshihiko Okayama
  • Patent number: 4550366
    Abstract: A programmable sequence controller and a sequence control system including a plurality of such controllers. Each sequence controller includes a program memory for storing a preprogrammed sequence of instructions for controlling a machine or part of a machine in response to the status of the machine or part being controlled. Each controller includes data transfer circuitry for receiving status data from another sequence controller on a common data bus and transmitting its own status data to all of the other sequence controllers on the common data bus. Each sequence controller includes an input-output (I/O) memory and an (I/O) flag memory for storing and keeping track of current status information from each of the plurality of controllers.
    Type: Grant
    Filed: August 12, 1982
    Date of Patent: October 29, 1985
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventors: Fumiyasu Toyama, Masaaki Murakoshi, Masanori Wakuda, Junichi Sasaki, Hirotoshi Watanabe, Tomio Yukawa, Yoshihiko Okayama
  • Patent number: 4441161
    Abstract: A programmable sequence control apparatus including a first memory device for storing sequence program instructions, an input/output device, a relay ladder operation device for executing logic operations for a relay ladder circuit having n rows and m columns (wherein n and m are positive integers) in accordance with the program instructions, and a control device for delivering control signals to the relay ladder operation device, is so constructed that the control device includes a memory device for storing contact data and branch data for one column j (wherein j=1, 2, . . .
    Type: Grant
    Filed: April 9, 1981
    Date of Patent: April 3, 1984
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventors: Junichi Sasaki, Yoshihiko Okayama
  • Patent number: 4432047
    Abstract: A programmable sequence control apparatus comprises a memory device for storing sequence program instructions, an input/output device for introducing input data and delivering output data therefrom, a ladder operation device for carrying out logic operations for a ladder circuit having n lines and m columns in accordance with said program instructions, and a control device for delivering control signals to the ladder operation device. The ladder operation device comprises a first memory device for storing contact data for each column of said ladder circuit, a second memory device for storing branch data for each column of said ladder circuit, and a gate device for executing logic operations for respective lines in each column based on the results of the logic operations executed for corresponding lines in a previous column, and on outputs from the first and second memory devices for delivering results of the operations for the logic operations of a subsequent column.
    Type: Grant
    Filed: May 12, 1981
    Date of Patent: February 14, 1984
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventor: Yoshihiko Okayama