Abstract: Semiconductor devices laterally surrounded by at least one dielectric material portion are formed over a substrate. At least one edge seal ring structure is formed around the semiconductor devices and the at least one dielectric material portion. One or more of the at least one edge seal ring structure has a horizontal cross-sectional profile that includes laterally-extending regions that extend laterally with a uniform width between an inner sidewall and an outer sidewall, and notch regions connecting neighboring pairs of the laterally-extending regions and having a greater width than the uniform width. Cavities in the laterally-extending regions are connected to cavities in the notch regions to allow outgassing from the material of the at least one edge seal ring structure.

Abstract: Semiconductor devices laterally surrounded by at least one dielectric material portion are formed over a substrate. At least one edge seal ring structure is formed around the semiconductor devices and the at least one dielectric material portion. One or more of the at least one edge seal ring structure has a horizontal cross-sectional profile that includes laterally-extending regions that extend laterally with a uniform width between an inner sidewall and an outer sidewall, and notch regions connecting neighboring pairs of the laterally-extending regions and having a greater width than the uniform width. Cavities in the laterally-extending regions are connected to cavities in the notch regions to allow outgassing from the material of the at least one edge seal ring structure.

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract: A water-borne primer coating composition including a water-borne non-chlorinated polyolefin resin (A), a water-borne polyurethane resin (B), a water-borne epoxy resin (C) and an internally crosslinked acrylic particle emulsion (D), wherein the content of resin (A) is 15 to 60%, the content of resin (B) is 10 to 50%, the content of resin (C) is 20 to 50%, and the content of emulsion (D) is 5 to 20%, all by weight on the solid equivalent basis in 100% by weight of the total amount of resin (A), resin (B), resin (C) and emulsion (D), and resin (A) is a polypropylene resin having crystallinity of 35 to 55% and a weight average molecular weight of 50000 to 200000. The composition can achieve an adhesion property to a substrate, gasohol resistance, inhibition of peeling of a multilayer coating film in washing by high pressure cleaning and moisture resistance.

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

Abstract: A laminate film has a clear layer (B) comprising an acrylic-based polymer (B1) having at least one longer unsaturated double bond group and at least one shorter unsaturated double bond group as side chains, and having a weight-average molecular weight not less than 50,000 but not more than 500,000, the longer unsaturated double bond group introduced in the acrylic-based polymer (B1) by a long-chain unsaturated carboxylic acid having a molecular weight of 150 or more, and the shorter unsaturated double bond group introduced in the acrylic-based polymer (B1) by a short-chain unsaturated carboxylic acid having a molecular weight of less than 150. Compared with laminate films prepared by spray coating, dip coating, or other coating methods, this laminate film is excellent in processability, coating film properties, and ornamental properties. Thus, an article can be excellently decorated with the laminate film provided by the present invention.

Abstract: A method for forming a bright coating film includes: (1) applying a water-based primer coating material composition to a substrate to form a water-based primer coating film; (2) applying a water-based bright coating material (i) to the water-based primer coating film to form a first base coating film; (3) applying a water-based bright coating material (ii) to the first base coating film to form a second base coating film; (4) applying a high-solid clear coating material to the second base coating film to form a clear coating film; and (5) heat-curing the water-based primer coating film, the first base coating film, the second base coating film, and the clear coating film simultaneously to form a cured coating film, wherein the water-based primer coating material composition includes a water-based non-chlorinated polyolefin resin (A), a water-based polyurethane resin (B), a water-based epoxy resin (C), and an internally crosslinked acrylic particle emulsion (D), and an emulsifier.

Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

Abstract: It is an object of the present invention to provide a water-borne primer coating composition using a polyolefin resin not containing chlorine, which can achieve an adhesion property to a substrate and gasohol resistance simultaneously and can achieve the inhibition of peeling of a multilayer coating film in washing a car by high pressure cleaning and moisture resistance simultaneously.

Abstract: The present invention to provide a water-borne coating composition for automotive interior substrates, which can form a coating film which is superior in an adhesion property on a plastic substrate by baking to dry at low temperatures of about 60° C., and can further attain a coating film which is also superior in a soft feeling, beef tallow resistance, chemical resistance and abrasion resistance. A water-borne coating composition for automotive interior substrates including a water-borne urethane resin (A), a water-borne chlorinated polyolefin modified acrylic resin (B), a water-borne polyolefin resin (C) and elastic particles (D), wherein the content of said resin (C) is 15 to 50% by weight when the total weight of said resin (A), resin (B) and resin (C) is taken as 100% by weight, a solid weight ratio [(A)/(B)] of said resin (A) and resin (B) is 90/10 to 50/50, said resin (A) has an elongation percentage of 100% or more at 20° C.

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract: An impurity is ion-implanted into the major surface of an Si substrate having a bulk microdefect density of 5×106 to 5×107 cm?3, a bulk microdefect size smaller than 100 nm, and a dissolved oxygen concentration of 1.1×1018 to 1.2×1018 cm?3. The Si substrate then undergoes ultra-rapid thermal annealing whose heating/cooling rate is higher than 1×105° C./sec, thereby electrically activating the impurity to form at least a partial impurity diffusion layer of a semiconductor element.