Patents by Inventor Yoshihiko Saito

Yoshihiko Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200300717
    Abstract: According to one embodiment, a pressure sensor is disclosed. The pressure sensor includes a substrate, and a first capacitor element. The first capacitor element includes a lower electrode provided on the substrate, an upper electrode disposed above the lower electrode, and a film provided over the lower electrode and upper electrode. The lower electrode and the upper electrode are between the substrate and the film. An absolute value of an amount of change in an electrostatic capacitance between the lower electrode and the upper electrode with respect to unit change in an ambient temperature of the first capacitor element is substantially zero.
    Type: Application
    Filed: September 11, 2019
    Publication date: September 24, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kei Masunishi, Naofumi Nakamura, Hiroaki Yamazaki, Tomohiro Saito, Fumitaka Ishibashi, Yoshihiko Kurui, Tomohiko Nagata
  • Publication number: 20200101640
    Abstract: Provided is a kneading device 1 for dispersing a dispersoid in a dispersion medium. The kneading device includes a casing in which a kneading material containing the dispersion medium and the dispersoid is accommodated, a rotor disposed in the casing and kneading the kneading material while dispersing the dispersoid in the dispersion medium by rotating about a rotation axis, and a detection unit detecting a dispersion degree of the dispersoid into the dispersion medium by observing a state of the kneading material in the casing.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Inventors: Hisashi Saito, Yoshihiko Nagata, Takamasa Kishima
  • Publication number: 20200045955
    Abstract: This composition can be easily added when cryopreserving cells and improves cell viability. 1 volume % of the composition containing 0.01 wt % to 20 wt % of a sophorose lipid is added just before or up to 6 hours before cryopreservation and cells are stored. This composition can improve cryopreservation cell viability as it reduces freezing damage to cells. With this composition, cells can be stored without using DMSO and blood serum. This is a simple and inexpensive storage method as it does not require fine control of the freezing rate during cell cryopreservation.
    Type: Application
    Filed: January 30, 2018
    Publication date: February 13, 2020
    Inventors: Asuka Nogami, Motoki Tatsumi, Nanase Ishii, Mizuyuki Ryu, Yoshihiko Hirata, Yoshiki Sawa, Shigeru Miyagawa, Atsuhiro Saito, Hirotatsu Ohkawara
  • Publication number: 20200039813
    Abstract: According to one embodiment, a MEMS device is disclosed. The MEMS device includes a substrate, and a MEMS vibrator provided on the substrate. The MEMS vibrator includes a first vibration portion disposed above the substrate, and a control electrode to control a vibration property of the first vibration portion. The control electrode is disposed without contacting the first vibration portion.
    Type: Application
    Filed: March 13, 2019
    Publication date: February 6, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Fujimoto, Yoshihiko Kurui, Hideyuki Tomizawa, Tomohiro Saito, Akihiro Kojima
  • Publication number: 20190256866
    Abstract: An mRNA forcibly expresses a protein gene in response to a miRNA, and a method for forcibly expressing the same, are provided. An artificial mRNA comprising a sequence encoding a protein gene, a miRNA target sequence linked to the 3?-terminal side of a Poly A sequence, and a translational repression sequence linked to the 3?-terminal side of the miRNA target sequence; and a method for expressing a protein gene in response to the expression of a miRNA, comprising a step of introducing the artificial mRNA into a cell.
    Type: Application
    Filed: June 27, 2017
    Publication date: August 22, 2019
    Applicant: KYOTO UNIVERSITY
    Inventors: Hirohide Saito, Yoshihiko Fujita
  • Patent number: 8637915
    Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
  • Patent number: 8324679
    Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: December 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
  • Patent number: 8282727
    Abstract: A water-borne primer coating composition including a water-borne non-chlorinated polyolefin resin (A), a water-borne polyurethane resin (B), a water-borne epoxy resin (C) and an internally crosslinked acrylic particle emulsion (D), wherein the content of resin (A) is 15 to 60%, the content of resin (B) is 10 to 50%, the content of resin (C) is 20 to 50%, and the content of emulsion (D) is 5 to 20%, all by weight on the solid equivalent basis in 100% by weight of the total amount of resin (A), resin (B), resin (C) and emulsion (D), and resin (A) is a polypropylene resin having crystallinity of 35 to 55% and a weight average molecular weight of 50000 to 200000. The composition can achieve an adhesion property to a substrate, gasohol resistance, inhibition of peeling of a multilayer coating film in washing by high pressure cleaning and moisture resistance.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: October 9, 2012
    Assignees: Honda Motor Co., Ltd., Nippon Bee Chemical Co., Ltd.
    Inventors: Takeshi Ogawa, Takanori Hashimoto, Emi Nomi, Yutaro Kawasaki, Yoshihiko Saito
  • Publication number: 20120181598
    Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
    Type: Application
    Filed: March 26, 2012
    Publication date: July 19, 2012
    Inventors: Masayuki ICHIGE, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
  • Patent number: 7982259
    Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: July 19, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
  • Publication number: 20110108905
    Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
    Type: Application
    Filed: January 14, 2011
    Publication date: May 12, 2011
    Inventors: Masayuki ICHIGE, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
  • Patent number: 7888730
    Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: February 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
  • Patent number: 7863166
    Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
  • Publication number: 20100112791
    Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
    Type: Application
    Filed: December 23, 2009
    Publication date: May 6, 2010
    Inventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
  • Patent number: 7651930
    Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: January 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
  • Patent number: 7531871
    Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: May 12, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Wataru Saito, Tsuneo Ogura, Hiromichi Ohashi, Yoshihiko Saito, Kenichi Tokano
  • Patent number: 7510769
    Abstract: A laminate film has a clear layer (B) comprising an acrylic-based polymer (B1) having at least one longer unsaturated double bond group and at least one shorter unsaturated double bond group as side chains, and having a weight-average molecular weight not less than 50,000 but not more than 500,000, the longer unsaturated double bond group introduced in the acrylic-based polymer (B1) by a long-chain unsaturated carboxylic acid having a molecular weight of 150 or more, and the shorter unsaturated double bond group introduced in the acrylic-based polymer (B1) by a short-chain unsaturated carboxylic acid having a molecular weight of less than 150. Compared with laminate films prepared by spray coating, dip coating, or other coating methods, this laminate film is excellent in processability, coating film properties, and ornamental properties. Thus, an article can be excellently decorated with the laminate film provided by the present invention.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: March 31, 2009
    Assignees: Nippon Bee Chemical Co., Ltd., Nippon Paint Co., Ltd., Hitachi Chemical Co., Ltd.
    Inventors: Takakazu Hase, Yoshihiko Saito, Koichi Takahashi, Yasushi Kojima, Kenichi Shinya, Keishi Hamada
  • Publication number: 20090041943
    Abstract: A method for forming a bright coating film includes: (1) applying a water-based primer coating material composition to a substrate to form a water-based primer coating film; (2) applying a water-based bright coating material (i) to the water-based primer coating film to form a first base coating film; (3) applying a water-based bright coating material (ii) to the first base coating film to form a second base coating film; (4) applying a high-solid clear coating material to the second base coating film to form a clear coating film; and (5) heat-curing the water-based primer coating film, the first base coating film, the second base coating film, and the clear coating film simultaneously to form a cured coating film, wherein the water-based primer coating material composition includes a water-based non-chlorinated polyolefin resin (A), a water-based polyurethane resin (B), a water-based epoxy resin (C), and an internally crosslinked acrylic particle emulsion (D), and an emulsifier.
    Type: Application
    Filed: August 8, 2008
    Publication date: February 12, 2009
    Applicants: HONDA MOTOR CO., LTD., NIPPON BEE CHEMICAL CO., LTD.
    Inventors: Takeshi OGAWA, Takanori HASHIMOTO, Emi NOMI, Yutaro KAWASAKI, Yoshihiko SAITO
  • Publication number: 20090004833
    Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 1, 2009
    Inventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
  • Publication number: 20080032055
    Abstract: It is an object of the present invention to provide a water-borne primer coating composition using a polyolefin resin not containing chlorine, which can achieve an adhesion property to a substrate and gasohol resistance simultaneously and can achieve the inhibition of peeling of a multilayer coating film in washing a car by high pressure cleaning and moisture resistance simultaneously.
    Type: Application
    Filed: July 30, 2007
    Publication date: February 7, 2008
    Applicants: HONDA MOTOR CO., LTD., NIPPON BEE CHEMICAL CO., LTD.
    Inventors: Takeshi OGAWA, Takanori HASHIMOTO, Emi NOMI, Yutaro KAWASAKI, Yoshihiko SAITO