Abstract: A signal delay device includes a delay unit including delay parts connected to one another in series and generating a delay signal; a selection unit to output the delay signal and including selectors connected to one another in series and outputting the delay signal, each selector receiving an output of one of the delay parts, being supplied with an output of former selector, and outputting the output of the delay part or the output of the former selector, based on a selection signal; a register unit holding delay setting data to set an amount of delay of the signal delay device; and a selection signal generator generating a selection signal indicating one of the selectors selecting an output of one of the delay parts based on the delay setting data and outputting the generated selection signal to the selection unit.

Abstract: A time difference measurement apparatus for measuring a time difference between transmission delay times of signals transmitted on two signal lines, includes: a selector for outputting one of the signals transmitted on the signal lines in accordance with a selection signal; a switch for outputting the selection signal in accordance with an output signal of the selector, the output signal being delayed for a predetermined time; a feedback loop for connecting the output of the selector to the input ends of the two signal lines; and a controller for calculating a time difference between transmission delay times of the signals transmitted on the two signal lines on the basis of self-oscillation cycles of signals transmitted through the feedback loop, the self-oscillation cycles changing in accordance with a logical value of the selection signal.

Abstract: According to an aspect of an embodiment, a logic circuit includes a first master latch included in one of the master-slave flip-flop circuits, the first master latch having a first scan data input for receiving scan data, the first master latch latching the scan data and outputting latched scan data, a second master latch included in another of the master-slave flip-flop circuits, the second master latch having a second scan data input operatively connected to receive an output of the first master latch, the second master latch latching the scan data inputted into the second scan data input and outputting latched scan data and a slave latch included in one of the master-slave flip-flop circuits, the slave latch having a scan data input operatively connected to receive an output of the second master latch.

Abstract: A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core for reference according to a first clock signal with a value captured in a taking-out scan chain to be tested through an operation of a processing core to be tested according to a second clock signal, a diagnosing unit which determines a timing failure in the logic circuit to be tested on the basis of a result of comparison by the comparator, and an adjuster which adjusts at least either a second cycle or a delay amount of the second clock signal. It is possible to examine a position of the timing failure or the number of the timing failures in the integrated circuit diagnosed as that its logic is normal but the timing failure occurs therein.

Abstract: Since fault detection is not conducted for the address other than the noted address or the expected value other than the noted expected value in the RAM test, generation of a fault can be discriminated easily for the predetermined noted address or noted expected value when a fault is detected. Moreover, since the noted address is set as a single address but as the predetermined address range, when a fault is generated after the test for the relevant address range, the total number of times of test can be controlled by conducting the screening test for the address range where a fault is generated.

Abstract: A layout structure for a CMOS circuit comprises a transistor layer forming P-type transistors 11 and 21 and N-type transistors 12 and 22, and a resistor layer which includes a resistor 13 formed to have a predetermined length and to make plural appropriate portions or the entire of the resistor along a direction of the length satisfy a mask rule necessary for providing VIAs, the resistor being connected to appropriate connecting portions of the P-type transistors and the N-type transistors through the VIAs by metal wires 31 formed of a metal layer, and the resistor having a predetermined circuit resistance which can be set based on the positions of the appropriate connecting portions.

Abstract: According to an aspect of an embodiment, a logic circuit includes a first master latch included in one of the master-slave flip-flop circuits, the first master latch having a first scan data input for receiving scan data, the first master latch latching the scan data and outputting latched scan data, a second master latch included in another of the master-slave flip-flop circuits, the second master latch having a second scan data input operatively connected to receive an output of the first master latch, the second master latch latching the scan data inputted into the second scan data input and outputting latched scan data and a slave latch included in one of the master-slave flip-flop circuits, the slave latch having a scan data input operatively connected to receive an output of the second master latch.

Abstract: A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core for reference according to a first clock signal with a value captured in a taking-out scan chain to be tested through an operation of a processing core to be tested according to a second clock signal, a diagnosing unit which determines a timing failure in the logic circuit to be tested on the basis of a result of comparison by the comparator, and an adjuster which adjusts at least either a second cycle or a delay amount of the second clock signal. It is possible to examine a position of the timing failure or the number of the timing failures in the integrated circuit diagnosed as that its logic is normal but the timing failure occurs therein.

Abstract: A flip-flop circuit having a majority-logic circuit is disclosed. The circuit further includes multiple master latches for writing in corresponding input signals, and one slave latch having an input connected to an output of the majority-logic circuit and an output connected to the inputs of the majority-logic circuit. The majority logic-circuit has multiple inputs connected to respective outputs of the master latches. During the period in which the master latches do not write in the corresponding input signals, an output signal of the majority-logic circuit is supplied to respective inputs of the master latches.

Abstract: Since fault detection is not conducted for the address other than the noted address or the expected value other than the noted expected value in the RAM test, generation of a fault can be discriminated easily for the predetermined noted address or noted expected value when a fault is detected. Moreover, since the noted address is set as a single address but as the predetermined address range, when a fault is generated after the test for the relevant address range, the total number of times of test can be controlled by conducting the screening test for the address range where a fault is generated.

Abstract: A temperature adaptive circuit is provided which can perform an ordinary operation of an LSI circuit in a predetermined temperature range by raising the temperature of the LSI circuit up to the predetermined temperature range. The temperature adaptive circuit includes the LSI circuit that selectively performs, based on an instruction, an ordinary operation, which is an operation in a temperature range where the LSI circuit operates normally, or a temperature rise operation, which is an operation of raising the temperature of the LSI circuit to the predetermined temperature range, and a motion control section that outputs an instruction for either of said ordinary operation and said temperature rise operation to said LSI circuit.

Abstract: A temperature adaptive circuit is provided which can perform an ordinary operation of an LSI circuit in a predetermined temperature range by raising the temperature of the LSI circuit up to the predetermined temperature range. The temperature adaptive circuit includes the LSI circuit that selectively performs, based on an instruction, an ordinary operation, which is an operation in a temperature range where the LSI circuit operates normally, or a temperature rise operation, which is an operation of raising the temperature of the LSI circuit to the predetermined temperature range, and a motion control section that outputs an instruction for either of said ordinary operation and said temperature rise operation to said LSI circuit.

Abstract: A layout structure for a CMOS circuit comprises a transistor layer forming P-type transistors 11 and 21 and N-type transistors 12 and 22, and a resistor layer which includes a resistor 13 formed to have a predetermined length and to make plural appropriate portions or the entire of the resistor along a direction of the length satisfy a mask rule necessary for providing VIAs, the resistor being connected to appropriate connecting portions of the P-type transistors and the N-type transistors through the VIAs by metal wires 31 formed of a metal layer, and the resistor having a predetermined circuit resistance which can be set based on the positions of the appropriate connecting portions.

Abstract: A flip-flop circuit having a majority-logic circuit is disclosed. The circuit further includes multiple master latches for writing in corresponding input signals, and one slave latch having an input connected to an output of the majority-logic circuit and an output connected to the inputs of the majority-logic circuit. The majority logic-circuit has multiple inputs connected to respective outputs of the master latches. During the period in which the master latches do not write in the corresponding input signals, an output signal of the majority-logic circuit is supplied to respective inputs of the master latches.