Patents by Inventor Yoshihiko Shindo
Yoshihiko Shindo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113471Abstract: A sealing element comprises a raised region. The raised region includes a plurality of first ridges on a first principal face, a plurality of second ridges on a second principal face opposite to the first principal face, and a central trough. The central trough is formed between the adjacent ones of the second ridges and is located in a center of the second principal face. At least one of the first ridges located in the most outer side of the plurality of first ridges is positioned offset in a width direction relative to the plurality of second ridges.Type: ApplicationFiled: October 4, 2023Publication date: April 4, 2024Applicant: Tyco Electronics Japan G.K.Inventor: Yoshihiko Shindo
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Publication number: 20230297239Abstract: A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.Type: ApplicationFiled: August 29, 2022Publication date: September 21, 2023Inventors: Kenta SHIBASAKI, Yoshihiko SHINDO, Yasuhiro HIRASHIMA, Akio SUGAHARA, Shigeki NAGASAKA, Dai NAKAMURA, Yousuke HAGIWARA
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Patent number: 11114792Abstract: A contact includes a pair of side walls, a front end upper wall extending from the side walls, a rear end upper wall extending from the side walls, a lance extending in a rearward direction from a rear end of the front end upper wall, and an extension piece extending in the rearward direction from a rear end portion of the lance. The lance has a catch portion at the rear end portion of the lance. The catch portion is caught in a housing when the contact is inserted into the housing. The extension piece is positioned under the rear end upper wall.Type: GrantFiled: December 20, 2019Date of Patent: September 7, 2021Assignee: Tyco Electronics Japan G.K.Inventor: Yoshihiko Shindo
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Publication number: 20200203876Abstract: A contact includes a pair of side walls, a front end upper wall extending from the side walls, a rear end upper wall extending from the side walls, a lance extending in a rearward direction from a rear end of the front end upper wall, and an extension piece extending in the rearward direction from a rear end portion of the lance. The lance has a catch portion at the rear end portion of the lance. The catch portion is caught in a housing when the contact is inserted into the housing. The extension piece is positioned under the rear end upper wall.Type: ApplicationFiled: December 20, 2019Publication date: June 25, 2020Applicant: Tyco Electronics Japan G.K.Inventor: Yoshihiko Shindo
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Patent number: 10511125Abstract: A connector comprises a wire cover and a lever pivotally attached to the wire cover. The wire cover has a cover lock and a cover biasing member. The lever is rotatable between an unmated position and a mated position. When the lever is in the mated position, the cover lock locks the lever in the mated position and the cover biasing member biases the lever toward the unmated position.Type: GrantFiled: August 29, 2017Date of Patent: December 17, 2019Assignee: Tyco Electronics Japan G.K.Inventor: Yoshihiko Shindo
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Patent number: 10141681Abstract: A waterproof connector comprises a housing, a waterproof member, and a lever. The waterproof member surrounds and contacts a sidewall of the housing over an entire circumference of the sidewall. The lever is movable between an unmated position and a mated position. In the mated position of the lever, the lever and the housing together cover the waterproof member over an entire circumference of the waterproof member.Type: GrantFiled: August 23, 2017Date of Patent: November 27, 2018Assignee: Tyco Electronics Japan G.K.Inventor: Yoshihiko Shindo
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Patent number: 10026491Abstract: A semiconductor memory device includes memory cells, a sense amplifier unit including a first latch circuit, and a control unit configured to execute read and write operations on the memory cells. The control unit, while executing the write operation on the memory cells, responsive to a write suspend command followed by a read command, performs a data saving operation, the read operation, and a data restoring operation prior to resuming the write operation. The data saving operation includes transferring first data stored in the first latch circuit to an external device, the first data including at least a result of verify operation performed on the memory cells. The data restoring operation includes transferring the first data to the first latch circuit.Type: GrantFiled: March 1, 2017Date of Patent: July 17, 2018Assignee: Toshiba Memory CorporationInventors: Yuko Utsunomiya, Takahiro Shimizu, Yoshihiko Shindo, Akio Sugahara, Toshio Yamamura
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Publication number: 20180075917Abstract: A semiconductor memory device includes memory cells, a sense amplifier unit including a first latch circuit, and a control unit configured to execute read and write operations on the memory cells. The control unit, while executing the write operation on the memory cells, responsive to a write suspend command followed by a read command, performs a data saving operation, the read operation, and a data restoring operation prior to resuming the write operation. The data saving operation includes transferring first data stored in the first latch circuit to an external device, the first data including at least a result of verify operation performed on the memory cells. The data restoring operation includes transferring the first data to the first latch circuit.Type: ApplicationFiled: March 1, 2017Publication date: March 15, 2018Inventors: Yuko UTSUNOMIYA, Takahiro SHIMIZU, Yoshihiko SHINDO, Akio SUGAHARA, Toshio YAMAMURA
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Publication number: 20180062304Abstract: A waterproof connector comprises a housing, a waterproof member, and a lever. The waterproof member surrounds and contacts a sidewall of the housing over an entire circumference of the sidewall. The lever is movable between an unmated position and a mated position. In the mated position of the lever, the lever and the housing together cover the waterproof member over an entire circumference of the waterproof member.Type: ApplicationFiled: August 23, 2017Publication date: March 1, 2018Applicant: Tyco Electronics Japan G.K.Inventor: Yoshihiko Shindo
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Publication number: 20180062312Abstract: A connector comprises a wire cover and a lever pivotally attached to the wire cover. The wire cover has a cover lock and a cover biasing member. The lever is rotatable between an unmated position and a mated position. When the lever is in the mated position, the cover lock locks the lever in the mated position and the cover biasing member biases the lever toward the unmated position.Type: ApplicationFiled: August 29, 2017Publication date: March 1, 2018Applicant: Tyco Electronics Japan G.K.Inventor: Yoshihiko Shindo
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Patent number: 9634420Abstract: An electrical connector has a retainer including a cantilever-type arm that operates with a small force. The retainer is held in the connector housing so as to be movable between a pre-latch position and a complete latch position, retaining terminals at the complete latch position. The retainer has: a first latch on the connector housing at the pre-latch position; a second latch on the connector housing at the complete latch position; a cantilever-type first elastic beam having a free end side formed with the pre-latch projection; and a second elastic beam having both ends supported by the first elastic beam and formed with the complete latch projection.Type: GrantFiled: September 9, 2015Date of Patent: April 25, 2017Assignee: Tyco Electronics Japan G.K.Inventors: Yoshihiko Shindo, Soichi Sakaguchi
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Publication number: 20160072212Abstract: An electrical connector has a retainer including a cantilever-type arm that operates with a small force. The retainer is held in the connector housing so as to be movable between a pre-latch position and a complete latch position, retaining terminals at the complete latch position. The retainer has: a first latch on the connector housing at the pre-latch position; a second latch on the connector housing at the complete latch position; a cantilever-type first elastic beam having a free end side formed with the pre-latch projection; and a second elastic beam having both ends supported by the first elastic beam and formed with the complete latch projection.Type: ApplicationFiled: September 9, 2015Publication date: March 10, 2016Applicant: TYCO ELECTRONICS JAPAN G.K.Inventors: Yoshihiko Shindo, Soichi Sakaguchi
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Patent number: 8616901Abstract: The invention has an object to provide a circuit board assembly for a circuit board, the circuit board assembly having a contact and a housing. The housing includes a contact holding plate having a receiving passageway located in a surface of the contact holding plate disposed perpendicular to a surface of a circuit board, and a contact securing portion. The contact includes a press-fit into and held by the contact securing portion of the receiving passageway, and having a board insertion portion positioned perpendicular to the surface of the circuit board inserted into the receiving passageway from a side of the board insertion portion with respect to the contact holding plate, and a housing insertion section extending in parallel to the surface of the circuit board inserted into the receiving passageway from a side of the board insertion portion with respect to the contact holding plate.Type: GrantFiled: December 27, 2011Date of Patent: December 31, 2013Assignee: Tyco Electronics Japan G.K.Inventor: Yoshihiko Shindo
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Publication number: 20120164851Abstract: The invention has an object to provide a circuit board assembly for a circuit board, the circuit board assembly having a contact and a housing. The housing includes a contact holding plate having a receiving passageway located n a surface of the contact holding plate disposed perpendicular to a surface of a circuit board, and a contact securing portion. The contact includes a press-fit into and held by the contact securing portion of the receiving passageway, and having a board insertion portion positioned perpendicular to the surface of the circuit board inserted into the receiving passageway from a side of the board insertion portion with respect to the contact holding plate, and a housing insertion section extending in parallel to the surface of the circuit board inserted into the receiving passageway from a side of the board insertion portion with respect to the contact holding plate.Type: ApplicationFiled: December 27, 2011Publication date: June 28, 2012Inventor: Yoshihiko Shindo
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Patent number: 8189395Abstract: A nonvolatile semiconductor memory that includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section. The data reading and programming control section includes: an adjacent memory cell data reading section; an adjacent memory cell data memory section; a reading voltage level control section; a data reading section for reading the data from a first memory cell at a plurality of reading voltages corresponding to a plurality of predetermined reading voltage verify levels controlled using the reading voltage level control section; and a data determining section for determining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.Type: GrantFiled: November 1, 2010Date of Patent: May 29, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Shiga, Susumu Fujimura, Yoshihiko Shindo
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Publication number: 20120122349Abstract: To provide an electrical connector in which the length at which contacts held protrude from the connector can be maintained even if the connector is deformed during processing. The electrical connector includes a plurality of contacts and a female housing. The female housing includes a mating connector receiving cavity, a receiving wall disposed along a bottom of the receiving cavity, a plurality of contact receiving passageways holding the plurality of contacts penetrating there through, and a protrusion protruding from the receiving wall into the receiving cavity.Type: ApplicationFiled: December 21, 2011Publication date: May 17, 2012Inventor: Yoshihiko Shindo
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Publication number: 20110044106Abstract: A nonvolatile semiconductor memory that includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section. The data reading and programming control section includes: an adjacent memory cell data reading section; an adjacent memory cell data memory section; a reading voltage level control section; a data reading section for reading the data from a first memory cell at a plurality of reading voltages corresponding to a plurality of predetermined reading voltage verify levels controlled using the reading voltage level control section; and a data determining section for determining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.Type: ApplicationFiled: November 1, 2010Publication date: February 24, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hitoshi SHIGA, Susumu Fujimura, Yoshihiko Shindo
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Patent number: 7843724Abstract: A nonvolatile semiconductor memory that includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section. The data reading and programming cortrol section includes: an adjacent memory cell data reading section; an adjacent memory cell data memory section; a reading voltage level control section; a data reading section for reading the data from a first memory cell at a plurality of reading voltages corresponding to a plurality of predetermined reading voltage verify levels controlled using the reading voltage level control section; and a data determining section for deterraining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.Type: GrantFiled: September 28, 2007Date of Patent: November 30, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Shiga, Susumu Fujimura, Yoshihiko Shindo
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Publication number: 20100037007Abstract: A nonvolatile semiconductor memory device includes a memory cell array in which memory cells having an electrically rewritable charge accumulation layer are arranged, a data writing/reading circuit that writes/reads data to/from the memory cell array in units of pages, a write state information storage circuit for nonvolatile storage of write state information indicating a data write state to the memory cell array by the data writing/reading circuit, and a control circuit that controls the data writing/reading circuit based on an access page address indicating a page from which data is about to be read by the data writing/reading circuit and write state information stored in the write state information storage circuit.Type: ApplicationFiled: August 3, 2009Publication date: February 11, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: TAKUYA FUTATSUYAMA, NAOYA TOKIWA, TOSHIAKI EDAHIRO, YOSHIHIKO SHINDO
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Publication number: 20080239805Abstract: A nonvolatile semiconductor memory according to the present invention includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section for, when performing 4-value data programming, read or erasure with respect to at least one of the plurality of memory cells, selecting and applying a voltage to a corresponding word line and a corresponding bit line among the plurality of word lines and the plurality of bit lines; wherein the data reading and programming control section includes an adjacent memory cell data reading section for reading, at a reading voltage of a predetermined reading voltage level, whether or not data is programmed in a lower page of a second memory cell adjacent to a first memory cell in the memory cell array, and generating adjacent memory cell state data which represents a data state of the second memory cell; an adjacType: ApplicationFiled: September 28, 2007Publication date: October 2, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hitoshi SHIGA, Susumu Fujimura, Yoshihiko Shindo