Patents by Inventor Yoshihiro Arimoto
Yoshihiro Arimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7674634Abstract: A semiconductor device incorporating a capacitor structure that includes a ferroelectric thin film is obtained by forming, on a single crystalline substrate 10 having a surface suited for growing thereon a thin film layer of ferroelectric single crystal having a plane (111), a ferroelectric single crystalline thin film 12? containing Pb and having a plane (111) 11 in parallel with the surface of the substrate (or a ferroelectric polycrystalline thin film containing Pb and oriented parallel with the plane (111) in parallel with the surface of the substrate) and part 16 of a circuit of a semiconductor device, to thereby fabricate the single crystalline substrate 10 having said ferroelectric thin film containing Pb and said part of the circuit of the semiconductor device; and bonding said single crystalline substrate 10 to another substrate on which the other circuit of the semiconductor device has been formed in advance, to couple the two circuits together.Type: GrantFiled: November 5, 2003Date of Patent: March 9, 2010Assignee: Fujitsu LimitedInventors: Kenji Maruyama, Masaki Kurasawa, Masao Kondo, Yoshihiro Arimoto
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Patent number: 7465980Abstract: A ferroelectric memory device includes a gate electrode formed on a semiconductor body via a ferroelectric film, first and second diffusion regions being formed in the semiconductor body at respective sides of a channel region, wherein the ferroelectric film comprises a first region located in the vicinity of the first diffusion region, a second region located in the vicinity of the second diffusion region, and a third region located between the first and second regions, wherein the first, second and third regions carry respective, mutually independent polarizations.Type: GrantFiled: September 8, 2005Date of Patent: December 16, 2008Assignees: Fujitsu Limited, Tokyo Institute of TechnologyInventors: Yoshihiro Arimoto, Hiroshi Ishihara, Tetsuro Tamura, Hiromasa Hoko, Koji Aizawa, Yoshiaki Tabuchi, Masaomi Yamaguchi, Yasuo Nara, Kazuhiro Takahashi, Satoshi Hasegawa
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Publication number: 20060166378Abstract: A semiconductor device incorporating a capacitor structure that includes a ferroelectric thin film is obtained by forming, on a single crystalline substrate 10 having a surface suited for growing thereon a thin film layer of ferroelectric single crystal having a plane (111), a ferroelectric single crystalline thin film 12? containing Pb and having a plane (111) 11 in parallel with the surface of the substrate (or a ferroelectric polycrystalline thin film containing Pb and oriented parallel with the plane (111) in parallel with the surface of the substrate) and part 16 of a circuit of a semiconductor device, to thereby fabricate the single crystalline substrate 10 having said ferroelectric thin film containing Pb and said part of the circuit of the semiconductor device; and bonding said single crystalline substrate 10 to another substrate on which the other circuit of the semiconductor device has been formed in advance, to couple the two circuits together.Type: ApplicationFiled: November 5, 2003Publication date: July 27, 2006Inventors: Kenji Maruyama, Masaki Kurasawa, Masao Kondo, Yoshihiro Arimoto
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Publication number: 20060081901Abstract: A ferroelectric memory device includes a gate electrode formed on a semiconductor body via a ferroelectric film, first and second diffusion regions being formed in the semiconductor body at respective sides of a channel region, wherein the ferroelectric film comprises a first region located in the vicinity of the first diffusion region, a second region located in the vicinity of the second diffusion region, and a third region located between the first and second regions, wherein the first, second and third regions carry respective, mutually independent polarizations.Type: ApplicationFiled: September 8, 2005Publication date: April 20, 2006Applicants: FUJITSU LIMTED, TOKYO INSTITUTE OF TECHNOLOGYInventors: Yoshihiro Arimoto, Hiroshi Ishihara, Tetsuro Tamura, Hiromasa Hoko, Koji Aizawa, Yoshiaki Tabuchi, Masaomi Yamaguchi, Yasuo Nara, Kazuhiro Takahashi, Satoshi Hasegawa
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Patent number: 6686048Abstract: A composite carbonaceous heat insulator which comprises a carbonaceous heat-insulating member having a bulk density of 0.1 to 0.4 g/cm3, a carbonaceous protecting layer having a bulk density of 0.3 to 2.0 g/cm3 and comprising a carbon fiber structure and a thermally decomposed carbon penetrated into the structure, and a thermally decomposed carbon coating layer having a bulk density higher than that of the carbonaceous protecting layer, wherein the above carbonaceous protecting layer is jointed to at least a part of the carbonaceous heat-insulating member to form a jointed body, and the thermally decomposed carbon coating layer is formed at least on the face of carbonaceous heat-insulating member in the surface of the jointed body; and a method for manufacturing the insulator. The heat insulator is reduced with respect to the depletion, deterioration and pulverization during the use thereof, while maintaining excellent insulating characteristics.Type: GrantFiled: November 26, 2001Date of Patent: February 3, 2004Assignee: Kureha Kagaku Kogyo K. K.Inventors: Yoshihiro Arimoto, Yukihiro Sibuya, Masanori Kobayashi, Shigeki Iwamoto
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Patent number: 6159858Abstract: A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.Type: GrantFiled: June 27, 1997Date of Patent: December 12, 2000Assignees: Fujitsu Limited, Mitsui Mining & Smelting Co., Ltd.Inventors: Sadahiro Kishii, Ko Nakamura, Yoshihiro Arimoto, Akiyoshi Hatada, Rintaro Suzuki, Naruo Ueda, Kenzo Hanawa
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Patent number: 6114247Abstract: A method of fabricating a semiconductor device includes a step of polishing a surface of a substrate by a chemical mechanical polishing process conducted on a polishing cloth by a slurry. The polishing is conducted so that projections having a height of about 30 .mu.m or less are formed on the polishing cloth with an interval of about 55 .mu.m or less as a result of the polishing.Type: GrantFiled: June 27, 1997Date of Patent: September 5, 2000Assignee: Fujitsu LimitedInventors: Ko Nakamura, Sadahiro Kishii, Yoshihiro Arimoto
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Patent number: 5904609Abstract: A polishing apparatus comprises a first surface plate for supporting a polishing object, a driving mechanism for rotating the first surface plate, a second surface plate arranged so as to oppose to the first surface plate, an abrasive cloth stuck to the second surface plate, a vibration detector attached to the first surface plate or the second surface plate for detecting vibration in polishing, a controlling portion for controlling polishing operation of the first surface plate and the second surface plate, and signal analyzing unit for analyzing vibration intensity detected by the a vibration detector through frequency analysis, integrating the vibration intensity relative to time, and transmitting a polishing stop signal to stop polishing operation of the first surface plate and the second surface plate to the controlling portion when variation in a resultant integral value relative to time is less than a first reference value or when the resultant integral value is less than a second reference value.Type: GrantFiled: April 25, 1996Date of Patent: May 18, 1999Assignee: Fujitsu LimitedInventors: Atsushi Fukuroda, Yoshihiro Arimoto, Ko Nakamura
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Patent number: 5877089Abstract: A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.Type: GrantFiled: January 27, 1998Date of Patent: March 2, 1999Assignee: Fujitsu LimitedInventors: Sadahiro Kishii, Akiyoshi Hatada, Rintaro Suzuki, Hiroshi Horie, Yoshihiro Arimoto, Ko Nakamura
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Patent number: 5763325Abstract: A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.Type: GrantFiled: July 2, 1996Date of Patent: June 9, 1998Assignee: Fujitsu LimitedInventors: Sadahiro Kishii, Akiyoshi Hatada, Rintaro Suzuki, Hiroshi Horie, Yoshihiro Arimoto, Ko Nakamura
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Patent number: 5760343Abstract: A combinational weighing system receives articles sequentially in a plurality of mutually parallel supply lines to be sequentially transported to weighing devices which are individually associated therewith and weigh batches of the articles received therefrom. Combinations of the measured weight values are combined and a particular combination of article batches is selected as having a total weight which satisfies a predefined condition. The article batches in the selected combination are transported in a general direction of flow from the weighing devices to an outlet in mutually different travel modes such that they are automatically aligned one behind another in the direction of flow as they are discharged together through the outlet.Type: GrantFiled: June 23, 1997Date of Patent: June 2, 1998Assignee: Ishida Co., Ltd.Inventors: Yoshihiro Arimoto, Kenzo Tsuzuike, Michihiko Yonetsu, Yoshiharu Asai
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Patent number: 5624300Abstract: For providing a method for polishing in which it is possible to polish a substance uniformly over a whole surface of a wafer without observing the polished surface of the wafer halfway through polishing, a wafer with current detective patterns formed of conductors directly contacted with a semiconductor substrate, and an insulating film covering the current detective patterns is held by a wafer holder with conductivity, and the insulating film is polished by a polisher in which a supporting plate with conductivity is exposed in openings through a polishing cloth while supplying a polishing slurry containing ions.Type: GrantFiled: July 10, 1996Date of Patent: April 29, 1997Assignee: Fujitsu LimitedInventors: Sadahiro Kishii, Yoshihiro Arimoto
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Patent number: 5621239Abstract: In a semiconductor device, first and second substrates are supported with respective first major surfaces in opposing, parallel and spaced relationship. A conductor layer of low resistivity material is provided on a selected one of the opposing and spaced major surfaces, in intimate contact and spaced from the opposed major surface of the other substrate. An active device is formed in the first substrate with a region electrically connected to the conductor layer. A contact region is exposed at the second major surface of the first substrate and extends through the first substrate and into electrical contact with the conductor layer.Type: GrantFiled: June 7, 1995Date of Patent: April 15, 1997Assignee: Fujitsu LimitedInventors: Hiroshi Horie, Atsushi Fukuroda, Yoshihiro Arimoto
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Patent number: 5562529Abstract: An apparatus and method for polishing a semiconductor wafer. A polisher includes a supporting plate having a conductive film and a polishing cloth formed on the conductive film of the supporting plate. The polishing cloth has a plurality of openings to expose the conductive film. A wafer holder has a conductive wafer holding surface to hold a semiconductor wafer having current detective patterns and an insulating film covering the current detective patterns. A polishing slurry supply device supplies a polishing slurry including ions to either the polishing cloth or the semiconductor wafer. A current detecting device, connected to the supporting plate and the wafer holder, detects a magnitude of a current flowing across the supporting plate and the wafer holder through the conductive wafer holding surface, the semiconductor wafer held by the wafer holder, the current detective patterns of the semiconductor wafer, the polishing slurry filled in the openings of the polishing cloth, and the conductive film.Type: GrantFiled: October 8, 1993Date of Patent: October 8, 1996Assignee: Fujitsu LimitedInventors: Sadahiro Kishii, Yoshihiro Arimoto, Hiroshi Horie, Fumitoshi Sugimoto
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Patent number: 5506433Abstract: A silicon-on-insulator (SOI) structure having a single crystal layer of a group III-V compound semiconductor material contacting a single crystal substrate of sapphire such that a principal surface of the single crystal layer establishes an intimate contact with a corresponding principal surface of the single crystal substrate and the single crystal layer, and the single crystal substrate are bonded with each other while elevating a temperature.Type: GrantFiled: August 24, 1994Date of Patent: April 9, 1996Assignee: Fujitsu LimitedInventors: Tatsuya Ohori, Isamu Hanyu, Fumitoshi Sugimoto, Yoshihiro Arimoto
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Patent number: 5413951Abstract: A method for fabricating an SOI structure which includes the steps of contacting a single crystal layer of a group III-V compound semiconductor material to a single crystal substrate of sapphire such that a principal surface of said single crystal layer establishes an intimate contact with a corresponding principal surface of said single crystal substrate and bonding the single crystal layer and the single crystal substrate with each other while elevating a temperature.Type: GrantFiled: February 19, 1993Date of Patent: May 9, 1995Assignee: Fujitsu LimitedInventors: Tatsuya Ohori, Isamu Hanyu, Fumitoshi Sugimoto, Yoshihiro Arimoto
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Patent number: 5399233Abstract: In a process of manufacturing a semiconductor substrate having a SOI (silicon on insulator) structure, grooves are formed in a silicon layer reduced in thickness to several microns so that the silicon layer is separated into island-like regions corresponding to a chip size or device regions, and a stopper having a thickness corresponding to a desired final thickness of the silicon layer is formed in the grooves. The silicon layer is scanned with a piece of polishing cloth which has an area larger than that of each island-like region but sufficiently smaller than that of silicon layer and which is attached to a pressing surface of the polishing jig, thereby polishing the silicon layer until the stopper is exposed. The thickness of the silicon layer is measured at a position such that the thickness of a portion thereof is measured immediately before the same portion is polished.Type: GrantFiled: February 1, 1993Date of Patent: March 21, 1995Assignee: Fujitsu LimitedInventors: Maki Murazumi, Yoshihiro Arimoto, Atsushi Fukuroda
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Patent number: 5037774Abstract: Process for the production of semiconductor devices by using silicon-on-insulator (SOI) techniques. The Si layers of the SOI structure include an interfacial layer of Si and a buffer layer of Si formed thereon, whereby the formation of stacking faults in the Si layers can be effectively prevented. Pretreatment of the underlying insulating material with a molybdate solution and interposition of an additional layer of slowly grown single-crystalline Si between the buffer layer of Si and the overlying active Si layer are also effective to inhibit the stacking faults. Semiconductor devices with high quality can be produced with good yield.Type: GrantFiled: July 15, 1987Date of Patent: August 6, 1991Assignee: Fujitsu LimitedInventors: Hideki Yamawaki, Yoshihiro Arimoto, Shigeo Kodama, Takafumi Kimura, Masaru Ihara