Patents by Inventor Yoshihiro Bessho

Yoshihiro Bessho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190278812
    Abstract: Taking as input a group of text pairs for learning in which each pair is constituted with a first text for learning and a second text for learning that serves as an answer when a question is made with the first text for learning, a query expansion model is learned so as to generate a text serving as an expanded query for a text serving as a query.
    Type: Application
    Filed: November 20, 2017
    Publication date: September 12, 2019
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Atsushi OTSUKA, Katsuji BESSHO, Kyosuke NISHIDA, Hisako ASANO, Yoshihiro MATSUO
  • Patent number: 7134198
    Abstract: A method for manufacturing an electric element built-in module including flip-chip mounting at least one electric element such as a semiconductor chip or a surface acoustic wave device on a wiring pattern, sealing the electric element with a thermosetting resin composition, and grinding or abrading the thermosetting resin composition and electric element from a side of the electric element opposite that of the wiring pattern. The method provides upper surfaces of the electric element and the thermosetting resin composition that are substantially flush with each other. The method provides an electric element built-in module suitable for high-density packaging with a reduced thickness without damaging the electric element and while maintaining mechanical strength.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: November 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Yoshihiro Bessho, Yasuhiro Sugaya, Keiji Onishi
  • Publication number: 20050017268
    Abstract: An object of the present invention is to provide a display apparatus that has, even when it is a large-sized one, a high manufacturing yield, as well as a simple structure as a whole including wirings.
    Type: Application
    Filed: September 9, 2002
    Publication date: January 27, 2005
    Inventors: Masahide Tsukamoto, Yoshihiro Bessho, Takeo Ukai
  • Patent number: 6818461
    Abstract: A mounting structure is formed by flip-chip mounting a semiconductor device onto a substrate. An electrical connecting portion of the semiconductor device is connected to an electrical connecting portion of the substrate by means of an electrically conductive adhesive. A region of the semiconductor device which is not involved in electrical connection is bonded to a region of the substrate which is not involved in electrical connection by means of an adhesive. A test of electrical properties is performed on the semiconductor device and the substrate which are connected to each other. If it is determined that the electrical properties are poor in the test, the semiconductor device is separated from the substrate after heating a bonding place of the adhesive up to a temperature higher than a glass transition point or a melting point of the adhesive. If it is determined that the electrical properties are good in the test, the semiconductor device and the substrate are sealed by means of a sealing resin.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: November 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuyoshi Amami, Tsukasa Shiraishi, Yoshihiro Bessho
  • Publication number: 20040212075
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Application
    Filed: May 20, 2004
    Publication date: October 28, 2004
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Patent number: 6798121
    Abstract: At least two electric elements (203) such as semiconductor chips or surface acoustic wave devices are mounted on wiring patterns (201), and the electric elements (203) are sealed with a thermosetting resin composition (204). An upper surface of the at least two electric elements (203) and an upper surface of the thermosetting resin composition (204) are abraded at the same time, thereby forming surfaces substantially flush with each other. Since they are abraded while being sealed with the thermosetting resin composition (204), it is possible to reduce the thickness without damaging the electric elements (203). Also, the electric elements (203) and the wiring patterns (201) can be prevented from being contaminated by an abrasive liquid. In this manner, it is possible to obtain an electric element built-in module whose thickness can be reduced while maintaining its mechanical strength.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: September 28, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Yoshihiro Bessho, Yasuhiro Sugaya, Keiji Onishi
  • Patent number: 6774316
    Abstract: The present invention aims to provide a wiring substrate highly reliable in insulation and connection and a method for manufacturing the wiring substrate. A wiring substrate having two or more wiring layers, insulation layers interposed between the neighboring wiring layers and containing an organic resin, and a via formed in the insulation layers and extended between neighboring wiring layers. The via including functional substances, as well as some of the voids (first voids) where at least the organic resins from the insulation layers exist and the remaining voids (second voids) where a gas exists.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: August 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Tatsuo Ogawa, Satoru Tomekawa, Yoshihiro Bessho, Tousaku Nishiyama, Tetsuyoshi Ogura
  • Patent number: 6756663
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Patent number: 6749889
    Abstract: In a mounting structure including a first electrode and a second electrode electrically connected to each other via a conductive adhesive, the periphery of an adhesion portion between at least one of the electrodes and the conductive adhesive is covered with an electrical insulating layer, whereby the adhesion portion is reinforced from the periphery. The electrical insulating layer may be formed by dissolving a binder resin component of the conductive adhesive in a solvent. This increases the concentration of a conductive filler in the conductive adhesive, so that the conductivity of the adhesion portion is also enhanced.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: June 15, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Takezawa, Tsutomu Mitani, Minehiro Itagaki, Yoshihiro Bessho, Kazuo Eda
  • Patent number: 6710682
    Abstract: A surface acoustic wave device of the present invention includes a piezoelectric substrate, a plurality of comb electrodes for exciting a surface acoustic wave, disposed on a principal plane of the piezoelectric substrate, a plurality of bumps disposed on the principal plane, and an insulating sheet disposed so as to be opposed to the principal plane, wherein the bumps and the comb electrodes are connected electrically to each other, and the bumps penetrate through the insulating sheet.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: March 23, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiji Onishi, Akihiro Nanba, Hiroki Sato, Katsunori Moritoki, Yoshihiro Bessho, Kunihiro Fujii, Kouzou Murakami
  • Publication number: 20040040740
    Abstract: At least two electric elements (203) such as semiconductor chips or surface acoustic wave devices are mounted on wiring patterns (201), and the electric elements (203) are sealed with a thermosetting resin composition (204). An upper surface of the at least two electric elements (203) and an upper surface of the thermosetting resin composition (204) are abraded at the same time, thereby forming surfaces substantially flush with each other. Since they are abraded while being sealed with the thermosetting resin composition (204), it is possible to reduce the thickness without damaging the electric elements (203). Also, the electric elements (203) and the wiring patterns (201) can be prevented from being contaminated by an abrasive liquid. In this manner, it is possible to obtain an electric element built-in module whose thickness can be reduced while maintaining its mechanical strength.
    Type: Application
    Filed: September 3, 2003
    Publication date: March 4, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Yoshihiro Bessho, Yasuhiro Sugaya, Keiji Onishi
  • Patent number: 6694613
    Abstract: A method for producing a printed-circuit board includes forming via holes that penetrate through a prepreg to whose surface a parting film is applied; filling the via holes with a conducting paste; compressing the prepreg under heat to cure the prepreg and the paste; and then peeling off the parting film. Thus, projection electrodes with a height corresponding to the thickness of the film are formed in a manner such that the projection electrodes are integrated with the via hole conductors.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: February 24, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshifumi Nakamura, Minehiro Itagaki, Hiroaki Takezawa, Yoshihiro Bessho, Tsukasa Shiraishi
  • Patent number: 6691409
    Abstract: A circuit board is configured so as to include not less than two wiring layers, an insulator layer for electric insulation between the wiring layers, and an inner-via-hole conductive member provided in the insulator layer in a thickness direction of the insulator layer, for electric connection between the wiring layers. The insulator layer is made of a composite material containing an organic resin and a material having a smaller thermal expansion coefficient than that of the organic resin, and includes a surface part, a core part, and a surface part laminated in the stated order, the surface part having a high content of the organic resin, the core part having a low content of the organic resin. The wiring layers have a land portion that is connected with the inner-via-hole conductive member, the land portion being embedded so as to be substantially in contact with the core part, and the inner-via-hole conductive member has a thickness substantially equal to a thickness of the core part.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: February 17, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Tatsuo Ogawa, Yoshihiro Bessho, Satoru Tomekawa, Yasuhiro Nakatani, Yoji Ueda, Susumu Matsuoka, Daizo Andoh, Fumio Echigo
  • Publication number: 20030207073
    Abstract: In a mounting structure including a first electrode and a second electrode electrically connected to each other via a conductive adhesive, the periphery of an adhesion portion between at least one of the electrodes and the conductive adhesive is covered with an electrical insulating layer, whereby the adhesion portion is reinforced from the periphery. The electrical insulating layer may be formed by dissolving a binder resin component of the conductive adhesive in a solvent. This increases the concentration of a conductive filler in the conductive adhesive, so that the conductivity of the adhesion portion is also enhanced.
    Type: Application
    Filed: April 7, 2003
    Publication date: November 6, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroaki Takezawa, Tsutomu Mitani, Minehiro Itagaki, Yoshihiro Bessho, Kazuo Eda
  • Patent number: 6603207
    Abstract: An electrode structure for a semiconductor device and a method for forming the electrode structure, and a mounted body including the semiconductor device are provided in which the semiconductor device can be easily connected to a circuit board with high reliability. An aluminum electrode is formed on an IC substrate. A passivation film is formed on the IC substrate so as to cover the peripheral portion of the aluminum electrode. A bump electrode is formed on the aluminum electrode by a wire bonding method. An aluminum oxide film is formed on the surface of the aluminum electrode that is exposed around the bump electrode. A conductive adhesive is applied as a bonding layer to the tip portion of the bump electrode of the semiconductor device by a transfer method or a printing method. The semiconductor device is aligned in the face-down state in such a manner that the bump electrode abuts on a terminal electrode of a circuit board, and is provided on a circuit board.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: August 5, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yoshihiro Bessho
  • Patent number: 6569512
    Abstract: In a mounting structure including a first electrode and a second electrode electrically connected to each other via a conductive adhesive, the periphery of an adhesion portion between at least one of the electrodes and the conductive adhesive is covered with an electrical insulating layer, whereby the adhesion portion is reinforced from the periphery. The electrical insulating layer may be formed by dissolving a binder resin component of the conductive adhesive in a solvent. This increases the concentration of a conductive filler in the conductive adhesive, so that the conductivity of the adhesion portion is also enhanced.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: May 27, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Takezawa, Tsutomu Mitani, Minehiro Itagaki, Yoshihiro Bessho, Kazuo Eda
  • Publication number: 20030094685
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Application
    Filed: January 8, 2003
    Publication date: May 22, 2003
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Publication number: 20030066683
    Abstract: A circuit board is configured so as to include not less than two wiring layers, an insulator layer for electric insulation between the wiring layers, and an inner-via-hole conductive member provided in the insulator layer in a thickness direction of the insulator layer, for electric connection between the wiring layers. The insulator layer is made of a composite material containing an organic resin and a material having a smaller thermal expansion coefficient than that of the organic resin, and includes a surface part, a core part, and a surface part laminated in the stated order, the surface part having a high content of the organic resin, the core part having a low content of the organic resin. The wiring layers have a land portion that is connected with the inner-via-hole conductive member, the land portion being embedded so as to be substantially in contact with the core part, and the inner-via-hole conductive member has a thickness substantially equal to a thickness of the core part.
    Type: Application
    Filed: October 25, 2002
    Publication date: April 10, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Tatsuo Ogawa, Yoshihiro Bessho, Satoru Tomekawa, Yasuhiro Nakatani, Yoji Ueda, Susumu Matsuoka, Daizo Andoh, Fumio Echigo
  • Patent number: 6538315
    Abstract: A semiconductor device has (a) a semiconductor component; (b) a circuit substrate; (c) a base material which is placed between the semiconductor component and the circuit substrate; and (d) a conductive paste, which is filled into a hole formed in the base material, for electrically connecting between a terminal electrode of the semiconductor component and an internal connection electrode of the circuit substrate.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: March 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Bessho, Minehiro Itagaki
  • Patent number: 6525414
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: February 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho