Patents by Inventor Yoshihiro Funato
Yoshihiro Funato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230343700Abstract: A semiconductor device includes a plurality of resistive films arranged on an interlayer dielectric film. Each of the plurality of resistive films extends in a first direction in plan view. The plurality of resistive films are arranged spaced apart in a second direction orthogonal to the first direction in plan view. The plurality of resistive films are divided into a first group, a second group, and a third group. The first group is located between the second group and the third group in the second direction. A second width variation amount of each of the plurality of second resistive films belonging to the second group and a third width variation amount of each of the plurality of third resistive films belonging to the third group are larger than a first width variation amount of each of the plurality of first resistive films belonging to the first group.Type: ApplicationFiled: February 2, 2023Publication date: October 26, 2023Inventors: Nobuhito SHIRAISHI, Yasuo MORIMOTO, Yoshihiro FUNATO
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Patent number: 10530383Abstract: In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.Type: GrantFiled: July 10, 2018Date of Patent: January 7, 2020Assignee: Renesas Electronics CorporationInventors: Kazuaki Kurooka, Yoshihiro Funato
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Patent number: 10145887Abstract: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.Type: GrantFiled: May 23, 2018Date of Patent: December 4, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuaki Kurooka, Yasuo Morimoto, Yoshihiro Funato
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Patent number: 10128861Abstract: An analog to digital (AD) converter includes an AD conversion circuit, and a calibration circuit that calibrates an output value of the AD conversion circuit. The calibration circuit includes a right-shift circuit that shifts an accumulated value of values obtained by removing a deviated value from a plurality of output values of the AD conversion circuit. The calibration circuit calibrates the output value of the AD conversion circuit based on the shifted value.Type: GrantFiled: April 13, 2018Date of Patent: November 13, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshihiro Funato, Yasuo Morimoto, Kazuaki Kurooka
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Publication number: 20180323797Abstract: In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.Type: ApplicationFiled: July 10, 2018Publication date: November 8, 2018Inventors: Kazuaki KUROOKA, Yoshihiro FUNATO
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Publication number: 20180267092Abstract: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.Type: ApplicationFiled: May 23, 2018Publication date: September 20, 2018Inventors: Kazuaki KUROOKA, Yasuo MORIMOTO, Yoshihiro FUNATO
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Patent number: 10075177Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.Type: GrantFiled: October 30, 2017Date of Patent: September 11, 2018Assignee: Renesas Electronics CorporationInventors: Yoshihiro Funato, Yasuo Morimoto
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Publication number: 20180234102Abstract: An analog to digital (AD) converter includes an AD conversion circuit, and a calibration circuit that calibrates an output value of the AD conversion circuit. The calibration circuit includes a right-shift circuit that shifts an accumulated value of values obtained by removing a deviated value from a plurality of output values of the AD conversion circuit. The calibration circuit calibrates the output value of the AD conversion circuit based on the shifted value.Type: ApplicationFiled: April 13, 2018Publication date: August 16, 2018Inventors: Yoshihiro Funato, Yasuo Morimoto, Kazuaki Kurooka
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Patent number: 10033397Abstract: In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.Type: GrantFiled: January 10, 2016Date of Patent: July 24, 2018Assignee: Renesas Electronics CorporationInventors: Kazuaki Kurooka, Yoshihiro Funato
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Patent number: 10006955Abstract: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.Type: GrantFiled: January 10, 2017Date of Patent: June 26, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuaki Kurooka, Yasuo Morimoto, Yoshihiro Funato
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Patent number: 9960779Abstract: An analog-to-digital (AD) convertor includes: an AD conversion circuit; and a correction circuit that corrects an output value of the AD conversion circuit based on a correction value, wherein the correction circuit generates a plurality of elemental correction values based on a plurality of output values which are converted values of a plurality of analog values by the AD conversion circuit, wherein the correction value is determined by an average value of remaining values obtained by removing a deviated value from the plurality of elemental correction values.Type: GrantFiled: October 31, 2017Date of Patent: May 1, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshihiro Funato, Yasuo Morimoto, Kazuaki Kurooka
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Publication number: 20180069563Abstract: An analog-to-digital (AD) convertor includes: an AD conversion circuit; and a correction circuit that corrects an output value of the AD conversion circuit based on a correction value, wherein the correction circuit generates a plurality of elemental correction values based on a plurality of output values which are converted values of a plurality of analog values by the AD conversion circuit, wherein the correction value is determined by an average value of remaining values obtained by removing a deviated value from the plurality of elemental correction values.Type: ApplicationFiled: October 31, 2017Publication date: March 8, 2018Inventors: Yoshihiro FUNATO, Yasuo MORIMOTO, Kazuaki KUROOKA
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Publication number: 20180054212Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.Type: ApplicationFiled: October 30, 2017Publication date: February 22, 2018Inventors: Yoshihiro FUNATO, Yasuo MORIMOTO
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Patent number: 9843340Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.Type: GrantFiled: December 26, 2016Date of Patent: December 12, 2017Assignee: Renesas Electronics CorporationInventors: Yoshihiro Funato, Yasuo Morimoto
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Patent number: 9838027Abstract: An analog-to-digital (AD) convertor includes: a capacitance digital-to-analog (DA) convertor circuit; a comparator circuit coupled to the capacitance DA convertor circuit; and a calibration circuit that calculates a correction value for the AD convertor, wherein the capacitance DA convertor circuit includes a first capacitor, a second capacitor, n number of capacitors (n being integer equal to or larger than 3), each of the capacitors from first to n-th to be activated based on input digital data, wherein each of the first and second capacitors is designed for having a first capacitance value, wherein the n-th capacitor is designed for having twice the capacitance value of the (n?1)-th capacitor, wherein the calibration circuit calculates the correction value based on first and second results of the AD convertor, and wherein the first result is generated using the n-th capacitor and the second result is generated using the capacitors from first to (n?1)-th.Type: GrantFiled: June 6, 2017Date of Patent: December 5, 2017Assignee: Renesas Electronics CorporationInventors: Yoshihiro Funato, Yasuo Morimoto, Kazuaki Kurooka
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Publication number: 20170272088Abstract: An analog-to-digital (AD) convertor includes: a capacitance digital-to-analog (DA) convertor circuit; a comparator circuit coupled to the capacitance DA convertor circuit; and a calibration circuit that calculates a correction value for the AD convertor, wherein the capacitance DA convertor circuit includes a first capacitor, a second capacitor, n number of capacitors (n being integer equal to or larger than 3), each of the capacitors from first to n-th to be activated based on input digital data, wherein each of the first and second capacitors is designed for having a first capacitance value, wherein the n-th capacitor is designed for having twice the capacitance value of the (n?1)-th capacitor, wherein the calibration circuit calculates the correction value based on first and second results of the AD convertor, and wherein the first result is generated using the n-th capacitor and the second result is generated using the capacitors from first to (n?1)-th.Type: ApplicationFiled: June 6, 2017Publication date: September 21, 2017Inventors: Yoshihiro FUNATO, Yasuo MORIMOTO, Kazuaki KUROOKA
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Publication number: 20170257112Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.Type: ApplicationFiled: December 26, 2016Publication date: September 7, 2017Inventors: Yoshihiro FUNATO, Yasuo MORIMOTO
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Publication number: 20170205458Abstract: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.Type: ApplicationFiled: January 10, 2017Publication date: July 20, 2017Inventors: Kazuaki KUROOKA, Yasuo MORIMOTO, Yoshihiro FUNATO
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Publication number: 20170194979Abstract: During a period of calibration of the ADC, the effect of unexpected external noise can be excluded. Provided is an analog to digital convertor including: an ADC that converts an analog value into a digital value; and an averaging circuit that calculates a correction value by a calibration operation. The converted value is corrected and output using the correction value being held in a normal operation. The analog to digital convertor is configured as follows. In the calibration operation, an elemental correction value on the basis of a converted value by the ADC corresponding to a predetermined analog value is supplied to the averaging circuit. The averaging circuit calculates the average value of the remaining elemental correction values obtained by removing the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value.Type: ApplicationFiled: December 6, 2016Publication date: July 6, 2017Inventors: Yoshihiro FUNATO, Yasuo MORIMOTO, Kazuaki KUROOKA
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Patent number: 9698804Abstract: During a period of calibration of the ADC, the effect of unexpected external noise can be excluded. Provided is an analog to digital convertor including: an ADC that converts an analog value into a digital value; and an averaging circuit that calculates a correction value by a calibration operation. The converted value is corrected and output using the correction value being held in a normal operation. The analog to digital convertor is configured as follows. In the calibration operation, an elemental correction value on the basis of a converted value by the ADC corresponding to a predetermined analog value is supplied to the averaging circuit. The averaging circuit calculates the average value of the remaining elemental correction values obtained by removing the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value.Type: GrantFiled: December 6, 2016Date of Patent: July 4, 2017Assignee: Renesas Electronics CorporationInventors: Yoshihiro Funato, Yasuo Morimoto, Kazuaki Kurooka