Patents by Inventor Yoshihiro Hamamatsu

Yoshihiro Hamamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8588335
    Abstract: A radio communication device which when transmitting both a first information sequence, on which ?/4-shift differential phase shift modulation is performed, as a delayed wave and a second information sequence, on which a differential phase shift modulation is performed, as an advance wave by using a PADM (Per transmit Antenna Differential Mapping) method, interchanges signal points respectively belonging to quadrants which are one of a first quadrant and a third quadrant, a second quadrant and a fourth quadrant, the first quadrant and the second quadrant, the first quadrant and the fourth quadrant, the second quadrant and the third quadrant, and the third quadrant and the fourth quadrant, the signal points being included in signal points mapped onto a complex plane which consists of a real number axis and an imaginary number axis, to change the arrangement of the information sequence.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: November 19, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshihiro Hamamatsu, Masaru Nobesawa, Koji Tomitsuka, Kenichiro Tanaka
  • Publication number: 20120140854
    Abstract: A radio communication device which when transmitting both a first information sequence, on which ?/4-shift differential phase shift modulation is performed, as a delayed wave and a second information sequence, on which a differential phase shift modulation is performed, as an advance wave by using a PADM method, interchanges signal points respectively belonging to quadrants which are one of a first quadrant and a third quadrant, a second quadrant and a fourth quadrant, the first quadrant and the second quadrant, the first quadrant and the fourth quadrant, the second quadrant and the third quadrant, and the third quadrant and the fourth quadrant, the signal points being included in signal points mapped onto a complex plane which consists of a real number axis and an imaginary number axis, to change the arrangement of the information sequence.
    Type: Application
    Filed: August 13, 2010
    Publication date: June 7, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoshihiro Hamamatsu, Masaru Nobesawa, Koji Tomitsuka, Kenichiro Tanaka
  • Patent number: 7557654
    Abstract: A linearizer changes a gain characteristic to a valley characteristic in which a gain reduces and then increases. The linearizer includes: a signal path in which an RF signal input terminal an input side bias blocking capacitor, a diode pair, including diodes having opposite polarities to each other, an output side bias blocking capacitor and an RF signal output terminal in series in the stated order; a bias circuit in which a resistor is provided between and a signal path formed between the input side bias blocking capacitor and the diode pair and a bias terminal; an RF short-circuiting capacitor whose one end is connected with the bias circuit between the bias terminal and the resistor and whose other end is grounded; and a DC feed inductor whose one end is connected with the signal path between the diode pair and the output side bias blocking capacitor and whose other end is grounded.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: July 7, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hifumi Noto, Kazuhisa Yamauchi, Yoshihiro Hamamatsu, Tomokazu Hamada, Masatoshi Nakayama
  • Publication number: 20070241815
    Abstract: A linearizer changes a gain characteristic to a valley characteristic in which a gain reduces and then increases. The linearizer includes: a signal path in which an RF signal input terminal (1), an input side bias blocking capacitor (4), a diode pair (8, 12) including diodes having opposite polarities to each other, an output side bias blocking capacitor (5), and an RF signal output terminal (2) in series in the stated order; a bias circuit in which a resistor is provided between and a signal path formed between the input side bias blocking capacitor (4) and the diode pair (8, 12) and a bias terminal (3); an RF short-circuiting capacitor (6) whose one end is connected with the bias circuit between the bias terminal (3) and the resistor (7) and whose other end is grounded; and a DC feed inductor (11) whose one end is connected with the signal path between the diode pair (8, 12) and the output side bias blocking capacitor (5) and whose other end is grounded.
    Type: Application
    Filed: October 28, 2004
    Publication date: October 18, 2007
    Inventors: Hifumi Noto, Kazuhide Yamauchi, Yoshihiro Hamamatsu, Tomokazu Hamada, Masatoshi Nakayama