Abstract: A writing unit divides a sync byte into two sync bytes of a first sync byte and a second sync byte and also divides write data into two data of first data and second data and writes them. When a first sync byte pattern is detected, a reading unit demodulates the subsequent first data, second data, and an error detection correction code. When the first sync byte pattern SB1 is not detected but a second sync byte pattern SB2 is detected, the subsequent second data and error detection correction code are demodulated and the first data is reconstructed by the error detection correction code.

Abstract: A writing unit writes a first sync byte pattern SB1 to the head of data and writes a second sync byte pattern SB2 to the end of the data (DATA+ECC). When the first sync byte pattern SB1 is not detected, the data is stored into a memory, and after that, a reading unit reads out the second sync byte pattern SB2 in the memory. When the second sync byte pattern SB2 is detected, the reading unit reads out the data of a predetermined length DL in which a position that is preceding to the detecting position by only a predetermined data length (DL) is set to the head position from the memory and demodulates.

Abstract: Disclosed is a PRML regenerating apparatus for regenerating a signal read by a head from a storage medium. This PRML regenerating apparatus has a waveform equalizing circuit for waveform-equalizing the read signal, a maximum-likelihood decoder for maximum-likelihood-decoding, after obtaining a determination value by comparing the equalized output with upper and lower slice levels, this determination value and a control circuit for setting variable a distance between the upper slice level and the lower slice level of the maximum-likelihood decoder. The distance between the upper and lower slice levels can be thereby set variable in accordance with an equalization characteristic. A ternary determination circuit of the maximum-likelihood decoder is constructed of a memory for storing a correspondence table of the equalized output and the upper or lower slice level versus the determination result and the next upper or lower slice level.

Abstract: Disclosed is a phase difference detection circuit for detecting a phase difference between an equalized signal obtained by equalizing an extended partial-response class-4 signal and a sampling clock. This phase difference detection circuit has a sample hold circuit for sampling and holding the equalized signal at the sampling clock, a comparator circuit for comparing the sampled and held signals with at least four slice levels and converting them into determination level signals having at least quinary values and a phase difference generation circuit for generating a phase difference on the basis of at least the quinary determination level signals from the comparator circuit and outputs of the sample hold circuit. The EPR-4 signals are quinary-determined, and it is therefore possible to measure the phase difference by accurately detecting a peak position or a zero cross position of the signal.