Abstract: An image processing apparatus includes an image capture apparatus with a reduced size for capturing still image data. An extracting circuit extracts at least an area of still image data. A dividing circuit divides the area extracted by the extracting circuit into a plurality of first through nth areas. A memory circuit has a storage capacity smaller than a storage capacity required to store the still image data, and stores at least a portion of the image data of the first through nth areas provided by the dividing circuit. A transfer circuit transfers the image data stored in the memory circuit to an external device.

Abstract: A processor judges, by a comparator, match between an address determined to be a breakpoint of the CPU core and an address of a data cache at which the CPU core accesses the data cache. The data cache outputs a cache hit signal indicating a result of detection of a cache hit/miss at the time of the access. Further, an AND circuit outputs a data break signal to the CPU core, based on a match judgment signal from the comparator and the cache hit signal from the data cache, and causes the CPU core to execute a break.

Abstract: In response to a direct memory access (DMA) request, a direct memory access controller (DMAC) performs reading at a host side at which a high-speed bus master is arranged. A bus bridge sends a dummy data to the DMAC, and performs reading at an input/output (I/O) side at which a low-speed slave device is arranged. In response to a following DMA request, the DMAC performs reading at the host side. The bus bridge sends a data read for a previous DMA request at the I/O side to the DMAC, and performs reading at the I/O side. Data that is read in response to a final DMA request at the I/O side is stored in a buffer inside the bus bridge. A central processing unit (CPU) reads a last read data from the buffer.

Abstract: A semiconductor device includes a clock generation unit which generates a clock signal, a first module which asserts a clock-control request signal, and one or more second modules, each of which receives the clock signal and the clock-control request signal, and asserts a clock-control acknowledge signal after stopping an operation thereof upon completion of a currently performed operation in response to the assertion of the clock-control request signal, wherein the clock generation unit selectively changes the clock signal supplied to the one or more second modules in response to assertion of all clock-control acknowledge signals output from the one or more second modules.

Abstract: In response to a direct memory access (DMA) request, a direct memory access controller (DMAC) performs reading at a host side at which a high-speed bus master is arranged. A bus bridge sends a dummy data to the DMAC, and performs reading at an input/output (I/O) side at which a low-speed slave device is arranged. In response to a following DMA request, the DMAC performs reading at the host side. The bus bridge sends a data read for a previous DMA request at the I/O side to the DMAC, and performs reading at the I/O side. Data that is read in response to a final DMA request at the I/O side is stored in a buffer inside the bus bridge. A central processing unit (CPU) reads a last read data from the buffer.

Abstract: The read position or write position of data is decided by the base address of a ring buffer and an offset from the base address and the offset is updated by the amount of DMA-transferred data. When the offset becomes equal to or more than a value that indicates a total amount of transferred data, the offset is reset to zero to generate an address for circulating through and accessing the ring buffer. Moreover, a stop address showing the stop position of the DMA transfer operation is set to update the stop address by the amount of data read from or written in the ring buffer without depending on the DMA transfer operation. When the offset coincides with the stop address, the DMA transfer operation is stopped.

Abstract: An image processing apparatus includes an image capture apparatus with a reduced size for capturing still image data. An extracting circuit extracts at least an area of still image data. A dividing circuit divides the area extracted by the extracting circuit into a plurality of first through nth areas. A memory circuit has a storage capacity smaller than a storage capacity required to store the still image data, and stores at least a portion of the image data of the first through nth areas provided by the dividing circuit. A transfer circuit transfers the image data stored in the memory circuit to an external device.

Abstract: A semiconductor device includes a clock generation unit which generates a clock signal, a first module which asserts a clock-control request signal, and one or more second modules, each of which receives the clock signal and the clock-control request signal, and asserts a clock-control acknowledge signal after stopping an operation thereof upon completion of a currently performed operation in response to the assertion of the clock-control request signal, wherein the clock generation unit selectively changes the clock signal supplied to the one or more second modules in response to assertion of all clock-control acknowledge signals output from the one or more second modules.

Abstract: The read position or write position of data is decided by the base address of a ring buffer and an offset from the base address and the offset is updated by the amount of DMA-transferred data. When the offset becomes equal to or more than a value that indicates a total amount of transferred data, the offset is reset to zero to generate an address for circulating through and accessing the ring buffer. Moreover, a stop address showing the stop position of the DMA transfer operation is set to update the stop address by the amount of data read from or written in the ring buffer without depending on the DMA transfer operation. When the offset coincides with the stop address, the DMA transfer operation is stopped.