Patents by Inventor Yoshihiro Kawakita

Yoshihiro Kawakita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7047629
    Abstract: A circuit board manufacturing method including the steps of forming a through hole on an insulator layer and then filling the through hole with a conductive paste; dispersing and forming a protective agent on an adhesion surface of a conductor foil so as to include adhesion surface regions where the protective agent does not exist; sticking the conductor foil to the insulator layer; and abutting a plurality of conductive powders constituting the conductive paste and the conductor foil to each other through the adhesion surface regions by means of heating and pressurizing the insulator layer and conductor foil.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: May 23, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Publication number: 20060064871
    Abstract: A pre-preg sheet including a substrate and a resin impregnated in the substrate is provided. A first metal foil is placed on the pre-preg sheet to provide a laminated body. The laminated body is put in a heating device having a temperature maintained at a temperature close to a softening temperature of the resin. The laminated body is compressed at the temperature at a predetermined pressure. The first metal foil is bonded to the pre-preg sheet of the laminated body and hardening the resin, thus providing a circuit board. This method provides a stable resistance of a conductive paste filling a through-hole in the pre-preg sheet to be compressed at a small rate.
    Type: Application
    Filed: November 30, 2004
    Publication date: March 30, 2006
    Inventors: Yoshihiro Kawakita, Toshiaki Takenaka, Tadashi Tojyo
  • Publication number: 20050198818
    Abstract: In a method of manufacturing a circuit forming board, a first sheet having a first direction is transferred in a second direction, so that the first direction of the first sheet is parallel to the second direction. Films are stuck onto both surfaces of the first sheet while transferring the first sheet in a third direction orthogonal to the first direction of the first sheet. This method allows connecting member, such as conductive paste, to electrically coupling between layers of the circuit forming board.
    Type: Application
    Filed: May 14, 2004
    Publication date: September 15, 2005
    Inventors: Toshihiro Nishii, Yoshihiro Kawakita, Kunio Kishimoto
  • Patent number: 6930395
    Abstract: A connecting strength at a bonding site between a wiring layer 1c and a conductor 1d is enhanced by comparing a bonding strength between a wiring layer 14 provided by covering the conductor 1d on an insulating base 1a and the conductor 1d with a bonding strength between the wiring layer 1c and the insulating base 1a in an adjacency of the conductor to set the latter relatively lower.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: August 16, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoru Tomekawa, Yoshihisa Yamashita, Takeshi Suzuki, Yoshihiro Kawakita, Tadashi Nakamura
  • Publication number: 20050139384
    Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.
    Type: Application
    Filed: February 18, 2005
    Publication date: June 30, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Satoru Tomekawa, Yoshihiro Kawakita, Yasushi Nakagiri, Fumio Echigo
  • Patent number: 6866892
    Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: March 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Satoru Tomekawa, Yoshihiro Kawakita, Yasushi Nakagiri, Fumio Echigo
  • Publication number: 20050006139
    Abstract: After disposing metallic foils on either surface of a prepreg sheet of low compressibility having conducting holes filled with conductive paste, the prepreg sheet is compressed in a state of being kept at a relatively low temperature, and after that, the temperature is raised under pressure to melt and harden the resin in the prepreg sheet, and thereby, the connecting resistance is stabilized, and a high-quality circuit board can be obtained.
    Type: Application
    Filed: December 26, 2003
    Publication date: January 13, 2005
    Inventors: Toshiaki Takenaka, Yoshihiro Kawakita, Tadashi Tojo, Kiyohide Tatsumi
  • Publication number: 20040142161
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Application
    Filed: January 9, 2004
    Publication date: July 22, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Patent number: 6734375
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: May 11, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Publication number: 20040080918
    Abstract: A protective agent 6 for protecting a wiring 1 is dispersed and placed in mottle-like on an interface between a via 3 and a wiring layer 2. Then, each dimension of interface regions 7 where the protective agent 6 does not exist is set to such a size that a plurality of conductive powders 4 constituting the via 3 can abutted on the wiring layer 2. Therefore, the plurality of conductive powders 4 and the wiring layer 2 are abutted each other in each interface region 7 where the protective agent 6 does not exist to electrically connect, thereby stabilizing the connection resistance for a prolonged period of time.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 29, 2004
    Applicant: MUTSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Patent number: 6713688
    Abstract: A protective agent 6 for protecting a wiring 1 is dispersed and placed in mottle-like on an interface between a via 3 and a wiring layer 2. Then, each dimension of interface regions 7 where the protective agent 6 does not exist is set to such a size that a plurality of conductive powders 4 constituting the via 3 can abutted on the wiring layer 2. Therefore, the plurality of conductive powders 4 and the wiring layer 2 are abutted each other in each interface region 7 where the protective agent 6 does not exist to electrically connect, thereby stabilizing the connection resistance for a prolonged period of time.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: March 30, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Publication number: 20040058136
    Abstract: A circuit board ensuring electrical connections is provided. An insulated board material, having connecting means for connecting a layer to another layer, includes a reinforcing member. A thickness of the entire insulated board material is at least equal to or not more than 1.5 times of a thickness of the reinforcing member.
    Type: Application
    Filed: July 29, 2003
    Publication date: March 25, 2004
    Inventors: Toshihiro Nishii, Yasuharu Fukui, Kiyohide Tatsumi, Yoshihiro Kawakita, Shinji Nakamura, Hideaki Komoda
  • Publication number: 20040005443
    Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.
    Type: Application
    Filed: June 27, 2003
    Publication date: January 8, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takeshi Suzuki, Satoru Tomekawa, Yoshihiro Kawakita, Yasushi Nakagiri, Fumio Echigo
  • Patent number: 6596381
    Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: July 22, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Satoru Tomekawa, Yoshihiro Kawakita, Yasushi Nakagiri, Fumio Echigo
  • Publication number: 20030045164
    Abstract: The present invention provides a nonwoven fabric material prepared from short fibers including thermal-resistant synthetic fibers bound with an inorganic binder, a prepreg and a circuit board using the same. The circuit board has an excellent dimensional stability even at a high temperature, and the circuit board is prevented from warping or being damaged by moisture absorption or the like. The inorganic binder is a residue formed from a low melting point glass solution or a water-dispersible colloidal solution including at least either fibers or particles of low melting point glass dispersed therein. When the binder is used, a chemical covalent bonding by a siloxane bonding is formed.
    Type: Application
    Filed: February 17, 2000
    Publication date: March 6, 2003
    Inventors: Fumio Echigo, Yoshihiro Kawakita
  • Publication number: 20020131248
    Abstract: A protective agent 6 for protecting a wiring 1 is dispersed and placed in mottle-like on an interface between a via 3 and a wiring layer 2. Then, each dimension of interface regions 7 where the protective agent 6 does not exist is set to such a size that a plurality of conductive powders 4 constituting the via 3 can abutted on the wiring layer 2. Therefore, the plurality of conductive powders 4 and the wiring layer 2 are abutted each other in each interface region 7 where the protective agent 6 does not exist to electrically connect, thereby stabilizing the connection resistance for a prolonged period of time.
    Type: Application
    Filed: November 8, 2001
    Publication date: September 19, 2002
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Publication number: 20020066961
    Abstract: A connecting strength at a bonding site between a wiring layer 1c and a conductor 1d is enhanced by comparing a bonding strength between a wiring layer 14 provided by covering the conductor 1d on an insulating base 1a and the conductor 1d with a bonding strength between the wiring layer 1c and the insulating base 1a in an adjacency of the conductor to set the latter relatively lower.
    Type: Application
    Filed: December 3, 2001
    Publication date: June 6, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoru Tomekawa, Yoshihisa Yamashita, Takeshi Suzuki, Yoshihiro Kawakita, Tadashi Nakamura
  • Publication number: 20020053465
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Application
    Filed: September 18, 2001
    Publication date: May 9, 2002
    Applicant: Matsushita electric Inductrial Co., Ltd.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Publication number: 20020037397
    Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.
    Type: Application
    Filed: September 26, 2001
    Publication date: March 28, 2002
    Applicant: Matsushita Electric Industrial Co. Ltd.
    Inventors: Takeshi Suzuki, Satoru Tomekawa, Yoshihiro Kawakita, Yasushi Nakagiri, Fumio Echigo
  • Patent number: 6205657
    Abstract: A printed circuit board includes insulating layers formed by impregnating a base material with a resin and a metal foil pattern formed on a desired layer of the insulating layers. Ions for forming a hardly soluble metal salt by combining with metal ions free from a portion of the board or a sulfur-containing compound for reacting with the metal ion are present in the insulating layer or on a surface of the metal foil pattern. Furthermore, a method for producing the printed circuit board includes any one of the steps of adding the ions or the sulfur-containing compound to the resin varnish, impregnating a base material with the solution of the ions or the sulfur-containing compound, or applying the solution onto the surface of the metal foil pattern, in order to allow the ions or the sulfur-containing compound to exist in the printed circuit board.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: March 27, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Kawakita, Seiichi Nakatani, Masakazu Tanahashi