Patents by Inventor Yoshihiro Kodaira

Yoshihiro Kodaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240075559
    Abstract: A solder material having a good thermal-cycle fatigue property and wettability. The solder material contains not less than 6.0% by mass and not more than 8.0% by mass Sb, not less than 3.0% by mass and not more than 5.0% by mass Ag, and the balance of Sn and incidental impurities. Also, a semiconductor device may include a joining layer between a semiconductor element and a substrate electrode or a lead frame, the joining layer being obtained by melting this solder material.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 7, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko WATANABE, Shunsuke SAITO, Yoshihiro KODAIRA
  • Patent number: 11850685
    Abstract: A solder material having a good thermal-cycle fatigue property and wettability. The solder material contains not less than 5.0% by mass and not more than 8.0% by mass Sb, not less than 3.0% by mass and not more than 5.0% by mass Ag, and the balance of Sn and incidental impurities. Also, a semiconductor device may include a joining layer between a semiconductor element and a substrate electrode or a lead frame, the joining layer being obtained by melting this solder material.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: December 26, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko Watanabe, Shunsuke Saito, Yoshihiro Kodaira
  • Publication number: 20230345637
    Abstract: A semiconductor device includes a first insulated circuit board that is rectangular with first to fourth sides, including a first input wiring board and a first output wiring board each extending in a first direction parallel to the first side and being adjacent to each other. The first output wiring board includes a first output region electrically connected to a first output terminal and a first connection wiring region electrically connected to the output electrodes of the plurality of first semiconductor chips and being closer to the second side than is the first output region. The first connection wiring region has a first slit extending in the first direction from an end of the first connection wiring region at a side thereof where the first output region is located.
    Type: Application
    Filed: March 13, 2023
    Publication date: October 26, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshihiro KODAIRA, Yusuke SEKINO, Taichi ITOH
  • Patent number: 11107787
    Abstract: A member for semiconductor device includes a metal portion configured to be bonded to another member by solder, and a treated coating covering a surface of the metal portion, the treated coating including a treatment agent. The treated coating vaporizes at a temperature lower than or equal to a solidus temperature of the solder.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: August 31, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinji Sano, Yoshihiro Kodaira, Masayuki Soutome, Kazunaga Onishi
  • Patent number: 10777473
    Abstract: Provided is a semiconductor device having: a terminal portion having a through hole is formed on a principal surface portion; and a casing portion in which an opening to make the principal surface portion of the terminal portion exposed is provided, wherein the opening has a corner portion corresponding to a corner of the principal surface portion of the terminal portion, wherein the casing portion has a thick portion, in which thickness of a resin may be greater than that of a middle portion between adjacent corner portions across two sides forming the corner portion, in a surrounding area of the opening. Furthermore, a slit portion extending outward from the corner portion may be formed in the casing portion. At least a part of the outline of the slit portion as viewed from the upper surface direction of the casing portion may be curved.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshihiro Kodaira
  • Patent number: 10522434
    Abstract: A semiconductor device is provided. The semiconductor device includes a terminal portion and a casing portion. The terminal portion has a through hole in a principal surface portion. The casing portion has a depression at a position facing the through hole and has an end surface facing portion facing an end surface of the terminal portion. An end surface protruding portion is provided on at least one of the end surface and the end surface facing portion.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 31, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshihiro Kodaira
  • Patent number: 10504868
    Abstract: The present invention suppresses fracture at an interface between different materials, and provides a solder joining which includes: a solder joining layer 10 having a melted solder material, containing Sb at more than 5.0% by mass and 10.0% by mass or less, Ag at 2.0 to 4.0% by mass, Ni at more than 0 and 1.0% by mass or less, and a balance made up of Sn and inevitable impurities; and joining members 11 and 123 at least one of which is a Cu or Cu-alloy member 123, in which the solder joining layer includes a first structure 1 containing (Cu, Ni)6(Sn, Sb)5 and a second structure 2 containing (Ni, Cu)3(Sn, Sb)X (in the formula, X is 1, 2, or 4) at an interface with the Cu or Cu-alloy member 123, and an electronic device and a semiconductor device including the solder joining.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: December 10, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko Watanabe, Shunsuke Saito, Yoshihiro Kodaira
  • Publication number: 20190193210
    Abstract: A solder material having a good thermal-cycle fatigue property and wettability. The solder material contains not less than 5.0% by mass and not more than 8.0% by mass Sb, not less than 3.0% by mass and not more than 5.0% by mass Ag, and the balance of Sn and incidental impurities. Also, a semiconductor device may include a joining layer between a semiconductor element and a substrate electrode or a lead frame, the joining layer being obtained by melting this solder material.
    Type: Application
    Filed: March 1, 2019
    Publication date: June 27, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko WATANABE, Shunsuke Saito, Yoshihiro Kodaira
  • Publication number: 20190157171
    Abstract: Provided is a semiconductor device having: a terminal portion having a through hole is formed on a principal surface portion; and a casing portion in which an opening to make the principal surface portion of the terminal portion exposed is provided, wherein the opening has a corner portion corresponding to a corner of the principal surface portion of the terminal portion, wherein the casing portion has a thick portion, in which thickness of a resin may be greater than that of a middle portion between adjacent corner portions across two sides forming the corner portion, in a surrounding area of the opening. Furthermore, a slit portion extending outward from the corner portion may be formed in the casing portion. At least a part of the outline of the slit portion as viewed from the upper surface direction of the casing portion may be curved.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 23, 2019
    Inventor: Yoshihiro KODAIRA
  • Patent number: 10297533
    Abstract: A semiconductor device is provided, including: a bottom portion having a pad formed of a conductive material; a lid portion covering at least a part of the bottom portion; and a first terminal portion and a second terminal portion which are provided in parallel with each other, are fixed to the lid portion, and each contact a corresponding pad, wherein: the first terminal portion is provided with a first plate-shaped portion; the second terminal portion is provided with a second plate-shaped portion; and each of the first plate-shaped portion and the second plate-shaped portion has a principal surface in a direction facing the pad and is flexible in a direction toward the pad.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshihiro Kodaira
  • Publication number: 20190081020
    Abstract: A member for semiconductor device includes a metal portion configured to be bonded to another member by solder, and a treated coating covering a surface of the metal portion, the treated coating including a treatment agent. The treated coating vaporizes at a temperature lower than or equal to a solidus temperature of the solder.
    Type: Application
    Filed: November 8, 2018
    Publication date: March 14, 2019
    Inventors: Shinji SANO, Yoshihiro KODAIRA, Masayuki SOUTOME, Kazunaga ONISHI
  • Patent number: 10153246
    Abstract: There is provided a method for producing a member for semiconductor device which can reduce generation of a large number of voids in a solder-bonded portion without increasing production cost. The method includes the step of preparing a first member including a metal portion capable of being bonded by solder and the step of coating the surface of the metal portion of the first member with a treatment agent to form a treated coating which vaporizes at a temperature lower than or equal to the solidus temperature of the solder.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 11, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinji Sano, Yoshihiro Kodaira, Masayuki Soutome, Kazunaga Onishi
  • Publication number: 20180277506
    Abstract: The present invention suppresses fracture at an interface between different materials, and provides a solder joining which includes: a solder joining layer 10 having a melted solder material, containing Sb at more than 5.0% by mass and 10.0% by mass or less, Ag at 2.0 to 4.0% by mass, Ni at more than 0 and 1.0% by mass or less, and a balance made up of Sn and inevitable impurities; and joining members 11 and 123 at least one of which is a Cu or Cu-alloy member 123, in which the solder joining layer includes a first structure 1 containing (Cu, Ni)6(Sn, Sb)5 and a second structure 2 containing (Ni, Cu)3(Sn, Sb)X (in the formula, X is 1, 2, or 4) at an interface with the Cu or Cu-alloy member 123, and an electronic device and a semiconductor device including the solder joining.
    Type: Application
    Filed: May 31, 2018
    Publication date: September 27, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko WATANABE, Shunsuke SAITO, Yoshihiro KODAIRA
  • Patent number: 10070527
    Abstract: When a nut housing member is inserted from a first opening portion into a case (terminal housing area) in a semiconductor device, first and second protrusions of the nut housing member slide on and pass through the first and second opening portions. Ultimately, the nut housing member is housed in the case (terminal housing area), with the first protrusion being in contact with a lower end of the second opening portion and the second protrusion being in contact with a lower end of the first opening portion. Even if the nut housing member is not inserted in parallel with the terminal housing area, the forefront does not hit against a first beam. Therefore, the nut housing member is inserted stably and housed reliably in the terminal housing area of the case, and the assemblability of the nut housing member with respect to the case is improved.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 4, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshihiro Kodaira
  • Publication number: 20180122715
    Abstract: A semiconductor device is provided. The semiconductor device includes a terminal portion and a casing portion. The terminal portion has a through hole in a principal surface portion. The casing portion has a depression at a position facing the through hole and has an end surface facing portion facing an end surface of the terminal portion. An end surface protruding portion is provided on at least one of the end surface and the end surface facing portion.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 3, 2018
    Inventor: Yoshihiro KODAIRA
  • Publication number: 20180122723
    Abstract: A semiconductor device is provided, including: a bottom portion having a pad formed of a conductive material; a lid portion covering at least a part of the bottom portion; and a first terminal portion and a second terminal portion which are provided in parallel with each other, are fixed to the lid portion, and each contact a corresponding pad, wherein: the first terminal portion is provided with a first plate-shaped portion; the second terminal portion is provided with a second plate-shaped portion; and each of the first plate-shaped portion and the second plate-shaped portion has a principal surface in a direction facing the pad and is flexible in a direction toward the pad.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 3, 2018
    Inventor: Yoshihiro KODAIRA
  • Patent number: 9941254
    Abstract: A semiconductor device 10 includes: multi-layered substrates 12 each having a circuit board 12c; control terminals 14 whose one end is fixed on the circuit board 12c of each multi-layered substrate 12; a resin case 15 which has openings 20 and is arranged to cover the multi-layered substrates 12, through which openings 20 the other ends of the control terminals 14 extend outwardly; and resin blocks 18 which are each inserted into the openings 20 of the resin case 15 and press-fixes the control terminals 14 against the side walls of the respective openings 20. The control terminals 14 each have a low-rigidity portion 14j at a position that is further interior of the resin case 15 than a position where each control terminal 14 is in contact with the resin block 18 in the respective openings 20 of the resin case 15.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 10, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshihiro Kodaira
  • Patent number: 9831152
    Abstract: A control terminal 14 of a semiconductor device has a recessed portion 14c. A resin case 15 is provided with a fixing member 152 engaging with and fixing a recessed portion 14c of a control terminal 14. The fixing member 152 is constituted by a resin block portion 154 having a step portion engaging with the recessed portion 14c, a nut-housing portion 153, and a beam portion 155 integrated by linking the resin block portion 154 and the nut-housing portion 153. A resin case main body 151 to which the fixing member 152 is fixed is provided with a hollow portion enabling insertion of the resin block portion 154. The nut-housing portion 153 of the fixing member 152 and the resin block portion 154 are attached to the resin case main body 151 from one direction.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 28, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Fumio Shigeta, Yoshihiro Kodaira
  • Publication number: 20170207187
    Abstract: There is provided a method for producing a member for semiconductor device which can reduce generation of a large number of voids in a solder-bonded portion without increasing production cost. The method includes the step of preparing a first member including a metal portion capable of being bonded by solder and the step of coating the surface of the metal portion of the first member with a treatment agent to form a treated coating which vaporizes at a temperature lower than or equal to the solidus temperature of the solder.
    Type: Application
    Filed: November 30, 2016
    Publication date: July 20, 2017
    Inventors: Shinji SANO, Yoshihiro KODAIRA, Masayuki SOUTOME, Kazunaga ONISHI
  • Publication number: 20170200704
    Abstract: A semiconductor device 10 includes: multi-layered substrates 12 each having a circuit board 12c; control terminals 14 whose one end is fixed on the circuit board 12c of each multi-layered substrate 12; a resin case 15 which has openings 20 and is arranged to cover the multi-layered substrates 12, through which openings 20 the other ends of the control terminals 14 extend outwardly; and resin blocks 18 which are each inserted into the openings 20 of the resin case 15 and press-fixes the control terminals 14 against the side walls of the respective openings 20. The control terminals 14 each have a low-rigidity portion 14j at a position that is further interior of the resin case 15 than a position where each control terminal 14 is in contact with the resin block 18 in the respective openings 20 of the resin case 15.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Inventor: Yoshihiro KODAIRA