Patents by Inventor Yoshihiro Matsuura

Yoshihiro Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9373593
    Abstract: A method of manufacturing a semiconductor device, includes providing a multi-chip interconnection substrate having an upper surface and a lower surface, providing a semiconductor chip having a main surface and a back surface, making the back surface of the semiconductor chip and the upper surface of the multi-chip interconnection substrate face each other and mounting the semiconductor chips in the chip mounting areas of the multi-chip interconnection substrate through a bonding adhesive, coupling the electrode pads formed on the main surface of each of the semiconductor chips with the bonding pads formed on the upper surface of the multi-chip interconnection substrate by the conductive wires respectively, forming a resin sealing body by resin-sealing the semiconductor chips, the conductive wires, and the upper surface of the multi-chip interconnection substrate, and forming a plurality of solder balls to be coupled to a plurality of bump lands formed on the lower surface of the multi-chip interconnection sub
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: June 21, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Sadao Nakayama, Yoshihiro Matsuura
  • Patent number: 9159681
    Abstract: A semiconductor device which uses a semiconductor chip originally designed for flip chip bonding and is assembled by a wire bonding process to reduce the cost of assembling a semiconductor product. A second electrode pad group and a fourth electrode pad group are located in the central area of the semiconductor chip and a first electrode pad group and a third electrode pad group are located adjacently to the two long sides of the semiconductor chip. The electrode pads of each electrode group are electrically coupled with a plurality of conductive wires. The layouts of the wiring layers formed in an interconnection substrate are modified so that the wire-bonded semiconductor device is the same as a flip-chip-bonded semiconductor device in terms of the positions of input/output signals.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: October 13, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Sadao Nakayama, Yoshihiro Matsuura
  • Publication number: 20150270244
    Abstract: A method of manufacturing a semiconductor device, includes providing a multi-chip interconnection substrate having an upper surface and a lower surface, providing a semiconductor chip having a main surface and a back surface, making the back surface of the semiconductor chip and the upper surface of the multi-chip interconnection substrate face each other and mounting the semiconductor chips in the chip mounting areas of the multi-chip interconnection substrate through a bonding adhesive, coupling the electrode pads formed on the main surface of each of the semiconductor chips with the bonding pads formed on the upper surface of the multi-chip interconnection substrate by the conductive wires respectively, forming a resin sealing body by resin-sealing the semiconductor chips, the conductive wires, and the upper surface of the multi-chip interconnection substrate, and forming a plurality of solder balls to be coupled to a plurality of bump lands formed on the lower surface of the multi-chip interconnection sub
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Inventors: Sadao NAKAYAMA, Yoshihiro MATSUURA
  • Publication number: 20140027919
    Abstract: A semiconductor device which uses a semiconductor chip originally designed for flip chip bonding and is assembled by a wire bonding process to reduce the cost of assembling a semiconductor product. A second electrode pad group and a fourth electrode pad group are located in the central area of the semiconductor chip and a first electrode pad group and a third electrode pad group are located adjacently to the two long sides of the semiconductor chip. The electrode pads of each electrode group are electrically coupled with a plurality of conductive wires. The layouts of the wiring layers formed in an interconnection substrate are modified so that the wire-bonded semiconductor device is the same as a flip-chip-bonded semiconductor device in terms of the positions of input/output signals.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 30, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Sadao Nakayama, Yoshihiro Matsuura
  • Patent number: 8039940
    Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
  • Patent number: 7790579
    Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: September 7, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
  • Publication number: 20080099883
    Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.
    Type: Application
    Filed: December 14, 2007
    Publication date: May 1, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kohji KANAMORI, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
  • Patent number: 7327019
    Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: February 5, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
  • Publication number: 20060180891
    Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.
    Type: Application
    Filed: April 6, 2006
    Publication date: August 17, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
  • Publication number: 20050218490
    Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.
    Type: Application
    Filed: March 14, 2005
    Publication date: October 6, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
  • Patent number: 6874922
    Abstract: The illumination device comprises at least one light source, and a light pipe positioned at the front side of a license plate, and a light diffusing means. A light of the light sources is led, the light pipe emitting a leading light from the surface of the license plate face. The light emitted from the observed face is diffused by the light diffusing means. The light diffusing means is provided with, rugged portions of an observed face opposite to a light emitting face, or, a light diffusing layer composed of two or more kinds of light transmitting materials, refractive indexes of which are different each other, on the observing face, and a light led from a light leading face is reflected and diffused on the light diffusing layer.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: April 5, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yoshihiro Matsuura, Tadanobu Iwasa, Akihiro Misawa, Yasumasa Tatewaki
  • Patent number: 6849950
    Abstract: Before a semiconductor chip (2) is mounted on package board (5), an insulating layer (3) is formed on the reverse side of the semiconductor chip (2) for preventing insulation failures. If the insulating layer (3) is formed by applying an insulating film, then the insulating layer (3) reliably achieves a predetermined thickness for reliable electric insulation and can easily be formed. The semiconductor chip (2) with the insulating layer (3) formed thereon is fixed to the package board (5) which has surface interconnections (7) by an insulating adhesive (adhesive layer 4). The semiconductor chip (2) and the surface interconnections (7) are insulated from each other by the insulating layer (3). Therefore, the adhesive may be used in a minimum quantity. Since the semiconductor chip (2) can be pressed under an increased pressure, the semiconductor chip (2) is reliably joined to the package board (5).
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: February 1, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Yoshihiro Matsuura
  • Publication number: 20030128549
    Abstract: The illumination device comprises at least one light source, and a light pipe positioned at the front side of a license plate, and a light diffusing means. A light of the light sources is led, the light pipe emitting a leading light from the surface of the license plate face. The light emitted from the observed face is diffused by the light diffusing means. The light diffusing means is provided with, rugged portions of an observed face opposite to a light emitting face, or, a light diffusing layer composed of two or more kinds of light transmitting materials, refractive indexes of which are different each other, on the observing face, and a light led from a light leading face is reflected and diffused on the light diffusing layer.
    Type: Application
    Filed: December 12, 2002
    Publication date: July 10, 2003
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Yoshihiro Matsuura, Tadanobu Iwasa, Akihiro Misawa, Yasumasa Tatewaki
  • Publication number: 20020079578
    Abstract: In a semiconductor device including an interposer substrate, a semiconductor chip, and an adhesive sheet for adhering the semiconductor chip to the interposer substrate, all outer periphery of the adhesive sheet is exposed to the outside.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 27, 2002
    Applicant: NEC CORPORATION
    Inventor: Yoshihiro Matsuura
  • Patent number: 5708372
    Abstract: In a semiconductor device in which power is supplied from an external power supply system, a first power supply system is connected to first terminals of power supply and ground and a digital inner circuit. The inner circuit includes a clock signal generating circuit, a driver for the clock signal, and circuits operating in response to the clock signal. A second power supply system is connected to second terminals of power supply and ground, the input terminal, the output terminal, and a digital interface circuit. The second power supply system is independent of the first power supply system. The interface circuit includes a MOS transistor for pulling up or down the input terminal and an output circuit which includes a MOS transistor driving an output terminal. The first power supply system is separated from the second power supply system, and the inner circuit is connected to the interface circuit through only signal lines.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: January 13, 1998
    Assignee: NEC Corporation
    Inventors: Hatsuhide Igarashi, Shigeru Takayama, Yoshihiro Matsuura, Hatsuhiro Nagaishi
  • Patent number: 5528728
    Abstract: Improved speaker independent speech recognition system and method are disclosed in which an utterance by an unspecified person into an electrical signal is input through a device such as a telephone, the electrical signal from the input telephone converting the electrical signal into a time series of characteristic multidimensional vectors, the time series of characteristic multidimensional vectors are received, each of the vectors being converted into a plurality of candidates so that the plurality of phonemes constitutes a plurality of strings of phonemes in time series as a plurality of candidates, the plurality of candidates of phonemes are compared simultaneously (one at a time) with a reference pattern of a reference string of phonemes for each word previously stored in a dictionary to determine which string of phonemes derived from the phoneme recognition means has a highest similarity to one of the reference strings of the phonemes for the respective words stored in the dictionary using a predetermine
    Type: Grant
    Filed: July 12, 1993
    Date of Patent: June 18, 1996
    Assignees: Kabushiki Kaisha Meidensha, Adaptive Solutions, Inc.
    Inventors: Yoshihiro Matsuura, Toby Skinner