Patents by Inventor Yoshihiro Matsuura
Yoshihiro Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9373593Abstract: A method of manufacturing a semiconductor device, includes providing a multi-chip interconnection substrate having an upper surface and a lower surface, providing a semiconductor chip having a main surface and a back surface, making the back surface of the semiconductor chip and the upper surface of the multi-chip interconnection substrate face each other and mounting the semiconductor chips in the chip mounting areas of the multi-chip interconnection substrate through a bonding adhesive, coupling the electrode pads formed on the main surface of each of the semiconductor chips with the bonding pads formed on the upper surface of the multi-chip interconnection substrate by the conductive wires respectively, forming a resin sealing body by resin-sealing the semiconductor chips, the conductive wires, and the upper surface of the multi-chip interconnection substrate, and forming a plurality of solder balls to be coupled to a plurality of bump lands formed on the lower surface of the multi-chip interconnection subType: GrantFiled: June 8, 2015Date of Patent: June 21, 2016Assignee: Renesas Electronics CorporationInventors: Sadao Nakayama, Yoshihiro Matsuura
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Patent number: 9159681Abstract: A semiconductor device which uses a semiconductor chip originally designed for flip chip bonding and is assembled by a wire bonding process to reduce the cost of assembling a semiconductor product. A second electrode pad group and a fourth electrode pad group are located in the central area of the semiconductor chip and a first electrode pad group and a third electrode pad group are located adjacently to the two long sides of the semiconductor chip. The electrode pads of each electrode group are electrically coupled with a plurality of conductive wires. The layouts of the wiring layers formed in an interconnection substrate are modified so that the wire-bonded semiconductor device is the same as a flip-chip-bonded semiconductor device in terms of the positions of input/output signals.Type: GrantFiled: July 23, 2013Date of Patent: October 13, 2015Assignee: Renesas Electronics CorporationInventors: Sadao Nakayama, Yoshihiro Matsuura
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Publication number: 20150270244Abstract: A method of manufacturing a semiconductor device, includes providing a multi-chip interconnection substrate having an upper surface and a lower surface, providing a semiconductor chip having a main surface and a back surface, making the back surface of the semiconductor chip and the upper surface of the multi-chip interconnection substrate face each other and mounting the semiconductor chips in the chip mounting areas of the multi-chip interconnection substrate through a bonding adhesive, coupling the electrode pads formed on the main surface of each of the semiconductor chips with the bonding pads formed on the upper surface of the multi-chip interconnection substrate by the conductive wires respectively, forming a resin sealing body by resin-sealing the semiconductor chips, the conductive wires, and the upper surface of the multi-chip interconnection substrate, and forming a plurality of solder balls to be coupled to a plurality of bump lands formed on the lower surface of the multi-chip interconnection subType: ApplicationFiled: June 8, 2015Publication date: September 24, 2015Inventors: Sadao NAKAYAMA, Yoshihiro MATSUURA
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Publication number: 20140027919Abstract: A semiconductor device which uses a semiconductor chip originally designed for flip chip bonding and is assembled by a wire bonding process to reduce the cost of assembling a semiconductor product. A second electrode pad group and a fourth electrode pad group are located in the central area of the semiconductor chip and a first electrode pad group and a third electrode pad group are located adjacently to the two long sides of the semiconductor chip. The electrode pads of each electrode group are electrically coupled with a plurality of conductive wires. The layouts of the wiring layers formed in an interconnection substrate are modified so that the wire-bonded semiconductor device is the same as a flip-chip-bonded semiconductor device in terms of the positions of input/output signals.Type: ApplicationFiled: July 23, 2013Publication date: January 30, 2014Applicant: Renesas Electronics CorporationInventors: Sadao Nakayama, Yoshihiro Matsuura
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Patent number: 8039940Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.Type: GrantFiled: December 14, 2007Date of Patent: October 18, 2011Assignee: Renesas Electronics CorporationInventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
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Patent number: 7790579Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.Type: GrantFiled: April 6, 2006Date of Patent: September 7, 2010Assignee: NEC Electronics CorporationInventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
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Publication number: 20080099883Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.Type: ApplicationFiled: December 14, 2007Publication date: May 1, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Kohji KANAMORI, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
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Patent number: 7327019Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.Type: GrantFiled: March 14, 2005Date of Patent: February 5, 2008Assignee: NEC Electronics CorporationInventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
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Publication number: 20060180891Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.Type: ApplicationFiled: April 6, 2006Publication date: August 17, 2006Applicant: NEC ELECTRONICS CORPORATIONInventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
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Publication number: 20050218490Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.Type: ApplicationFiled: March 14, 2005Publication date: October 6, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
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Patent number: 6874922Abstract: The illumination device comprises at least one light source, and a light pipe positioned at the front side of a license plate, and a light diffusing means. A light of the light sources is led, the light pipe emitting a leading light from the surface of the license plate face. The light emitted from the observed face is diffused by the light diffusing means. The light diffusing means is provided with, rugged portions of an observed face opposite to a light emitting face, or, a light diffusing layer composed of two or more kinds of light transmitting materials, refractive indexes of which are different each other, on the observing face, and a light led from a light leading face is reflected and diffused on the light diffusing layer.Type: GrantFiled: December 12, 2002Date of Patent: April 5, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Yoshihiro Matsuura, Tadanobu Iwasa, Akihiro Misawa, Yasumasa Tatewaki
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Patent number: 6849950Abstract: Before a semiconductor chip (2) is mounted on package board (5), an insulating layer (3) is formed on the reverse side of the semiconductor chip (2) for preventing insulation failures. If the insulating layer (3) is formed by applying an insulating film, then the insulating layer (3) reliably achieves a predetermined thickness for reliable electric insulation and can easily be formed. The semiconductor chip (2) with the insulating layer (3) formed thereon is fixed to the package board (5) which has surface interconnections (7) by an insulating adhesive (adhesive layer 4). The semiconductor chip (2) and the surface interconnections (7) are insulated from each other by the insulating layer (3). Therefore, the adhesive may be used in a minimum quantity. Since the semiconductor chip (2) can be pressed under an increased pressure, the semiconductor chip (2) is reliably joined to the package board (5).Type: GrantFiled: June 27, 2000Date of Patent: February 1, 2005Assignee: NEC Electronics CorporationInventor: Yoshihiro Matsuura
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Publication number: 20030128549Abstract: The illumination device comprises at least one light source, and a light pipe positioned at the front side of a license plate, and a light diffusing means. A light of the light sources is led, the light pipe emitting a leading light from the surface of the license plate face. The light emitted from the observed face is diffused by the light diffusing means. The light diffusing means is provided with, rugged portions of an observed face opposite to a light emitting face, or, a light diffusing layer composed of two or more kinds of light transmitting materials, refractive indexes of which are different each other, on the observing face, and a light led from a light leading face is reflected and diffused on the light diffusing layer.Type: ApplicationFiled: December 12, 2002Publication date: July 10, 2003Applicant: Toyoda Gosei Co., Ltd.Inventors: Yoshihiro Matsuura, Tadanobu Iwasa, Akihiro Misawa, Yasumasa Tatewaki
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Publication number: 20020079578Abstract: In a semiconductor device including an interposer substrate, a semiconductor chip, and an adhesive sheet for adhering the semiconductor chip to the interposer substrate, all outer periphery of the adhesive sheet is exposed to the outside.Type: ApplicationFiled: December 21, 2001Publication date: June 27, 2002Applicant: NEC CORPORATIONInventor: Yoshihiro Matsuura
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Patent number: 5708372Abstract: In a semiconductor device in which power is supplied from an external power supply system, a first power supply system is connected to first terminals of power supply and ground and a digital inner circuit. The inner circuit includes a clock signal generating circuit, a driver for the clock signal, and circuits operating in response to the clock signal. A second power supply system is connected to second terminals of power supply and ground, the input terminal, the output terminal, and a digital interface circuit. The second power supply system is independent of the first power supply system. The interface circuit includes a MOS transistor for pulling up or down the input terminal and an output circuit which includes a MOS transistor driving an output terminal. The first power supply system is separated from the second power supply system, and the inner circuit is connected to the interface circuit through only signal lines.Type: GrantFiled: June 5, 1996Date of Patent: January 13, 1998Assignee: NEC CorporationInventors: Hatsuhide Igarashi, Shigeru Takayama, Yoshihiro Matsuura, Hatsuhiro Nagaishi
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Patent number: 5528728Abstract: Improved speaker independent speech recognition system and method are disclosed in which an utterance by an unspecified person into an electrical signal is input through a device such as a telephone, the electrical signal from the input telephone converting the electrical signal into a time series of characteristic multidimensional vectors, the time series of characteristic multidimensional vectors are received, each of the vectors being converted into a plurality of candidates so that the plurality of phonemes constitutes a plurality of strings of phonemes in time series as a plurality of candidates, the plurality of candidates of phonemes are compared simultaneously (one at a time) with a reference pattern of a reference string of phonemes for each word previously stored in a dictionary to determine which string of phonemes derived from the phoneme recognition means has a highest similarity to one of the reference strings of the phonemes for the respective words stored in the dictionary using a predetermineType: GrantFiled: July 12, 1993Date of Patent: June 18, 1996Assignees: Kabushiki Kaisha Meidensha, Adaptive Solutions, Inc.Inventors: Yoshihiro Matsuura, Toby Skinner