Abstract: A noise removal circuit is provided having a first holding circuit (20) and a second holding circuit (22) which holds a value of an input signal (IN) at a plurality of different timings in synchronization with rising and falling of an internal clock signal (ICL) generated within a semiconductor device, and which removes noise of the input signal (IN) according to the held value.

Abstract: A noise removal circuit is provided having a first holding circuit (20) and a second holding circuit (22) which holds a value of an input signal (IN) at a plurality of different timings in synchronization with rising and falling of an internal clock signal (ICL) generated within a semiconductor device, and which removes noise of the input signal (IN) according to the held value.

Abstract: An interface circuit comprising: a first output circuit configured to allow an access signal to be input thereto and output the access signal to a storage circuit, the access signal capable of being changed to one logic level or the other logic level for accessing the storage circuit; a second output circuit configured to output the access signal outputted from the first output circuit; and a comparison circuit configured to compare the number of times a logic level of the access signal inputted to the first output circuit is changed and the number of times a logic level of the access signal outputted from the second output circuit is changed, and output a comparison signal indicating whether predetermined access has been performed based on the access signal inputted to the first output circuit, after at least a part of the access signal is inputted to the first output circuit.

Abstract: An interface circuit comprising: a first output circuit configured to allow an access signal to be input thereto and output the access signal to a storage circuit, the access signal capable of being changed to one logic level or the other logic level for accessing the storage circuit; a second output circuit configured to output the access signal outputted from the first output circuit; and a comparison circuit configured to compare the number of times a logic level of the access signal inputted to the first output circuit is changed and the number of times a logic level of the access signal outputted from the second output circuit is changed, and output a comparison signal indicating whether predetermined access has been performed based on the access signal inputted to the first output circuit, after at least a part of the access signal is inputted to the first output circuit.