Patents by Inventor Yoshihiro Nagai
Yoshihiro Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10204690Abstract: A semiconductor memory device according to the present invention includes a first memory cell, a second memory cell, a dummy transistor, and a voltage control circuit. The first memory cell has a first transistor that is coupled to a first word line, a first source line, and a bit line. The second memory cell has a second transistor that is coupled to a second word line, a second source line, and the bit line. The dummy transistor has the same structure as the first transistor and is coupled to a dummy word line, a dummy source line, and a dummy bit line. When a predetermined voltage for writing data into the first memory cell is to be applied to the first word line, the voltage control circuit couples the dummy bit line to the second source line and applies the predetermined voltage to the first dummy word line.Type: GrantFiled: October 17, 2017Date of Patent: February 12, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshihiro Nagai, Masami Hanyu, Yuka Suzuki
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Publication number: 20180053561Abstract: A semiconductor memory device according to the present invention includes a first memory cell, a second memory cell, a dummy transistor, and a voltage control circuit. The first memory cell has a first transistor that is coupled to a first word line, a first source line, and a bit line. The second memory cell has a second transistor that is coupled to a second word line, a second source line, and the bit line. The dummy transistor has the same structure as the first transistor and is coupled to a dummy word line, a dummy source line, and a dummy bit line. When a predetermined voltage for writing data into the first memory cell is to be applied to the first word line, the voltage control circuit couples the dummy bit line to the second source line and applies the predetermined voltage to the first dummy word line.Type: ApplicationFiled: October 17, 2017Publication date: February 22, 2018Inventors: Yoshihiro NAGAI, Masami HANYU, Yuka SUZUKI
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Patent number: 9818489Abstract: A semiconductor memory device according to the present invention includes a first memory cell, a second memory cell, a dummy transistor, and a voltage control circuit. The first memory cell has a first transistor that is coupled to a first word line, a first source line, and a bit line. The second memory cell has a second transistor that is coupled to a second word line, a second source line, and the bit line. The dummy transistor has the same structure as the first transistor and is coupled to a dummy word line, a dummy source line, and a dummy bit line. When a predetermined voltage for writing data into the first memory cell is to be applied to the first word line, the voltage control circuit couples the dummy bit line to the second source line and applies the predetermined voltage to the first dummy word line.Type: GrantFiled: February 4, 2017Date of Patent: November 14, 2017Assignee: Renesas Electronics CorporationInventors: Yoshihiro Nagai, Masami Hanyu, Yuka Suzuki
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Publication number: 20170278578Abstract: A semiconductor memory device according to the present invention includes a first memory cell, a second memory cell, a dummy transistor, and a voltage control circuit. The first memory cell has a first transistor that is coupled to a first word line, a first source line, and a bit line. The second memory cell has a second transistor that is coupled to a second word line, a second source line, and the bit line. The dummy transistor has the same structure as the first transistor and is coupled to a dummy word line, a dummy source line, and a dummy bit line. When a predetermined voltage for writing data into the first memory cell is to be applied to the first word line, the voltage control circuit couples the dummy bit line to the second source line and applies the predetermined voltage to the first dummy word line.Type: ApplicationFiled: February 4, 2017Publication date: September 28, 2017Inventors: Yoshihiro NAGAI, Masami HANYU, Yuka SUZUKI
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Patent number: 8106703Abstract: Booster circuit comprising: first transistor that is connected to first node; capacitor that has one end connected to first node, and that is charged with voltage of first node when first transistor is activated; and control signal generating circuit that provides control terminal of first transistor with control signal being in accordance with first clock, wherein when first transistor is de-activated, capacitor boosts voltage of first node to first voltage by voltage being applied to or end of capacitor, voltage applied to or end being at least ½ as great as first supply voltage, and control signal generating circuit sets voltage of control signal when first transistor is de-activated to be first voltage of first node, and sets voltage of control signal when first transistor is activated to be voltage, difference between voltage and first voltage being equal to or smaller than value of first supply voltage.Type: GrantFiled: May 10, 2010Date of Patent: January 31, 2012Assignees: Renesas Electronics Corporation, Toyota Jidosha Kabushiki KaishaInventors: Yoshihiro Nagai, Masakazu Amanai, Masahiko Kashimura, Masato Taki, Norihiro Honda, Kazushi Yamanaka
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Patent number: 8004902Abstract: A nonvolatile memory device includes a memory cell that stores data by presence or absence of electrons accumulated in a floating gate, a read reference current generator that generates a read reference current for reading data from the memory cell based on a constant current from a constant current generator included therein, and a read voltage generator that generates a read voltage to be applied to a control gate of the memory cell during data reading. The read reference current generator generates a monitor voltage that varies according to variation of the read reference current and a threshold voltage of the memory cell. The read voltage generator generates the read voltage based on the monitor voltage.Type: GrantFiled: November 17, 2009Date of Patent: August 23, 2011Assignees: Renesas Electronics Corporation, Toyota Jidosha Kabushiki KaishaInventors: Masakazu Amanai, Masahiko Kashimura, Yoshihiro Nagai, Masato Taki, Norihiro Honda, Kazushi Yamanaka
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Publication number: 20100301927Abstract: Booster circuit comprising: first transistor that is connected to first node; capacitor that has one end connected to first node, and that is charged with voltage of first node when first transistor is activated; and control signal generating circuit that provides control terminal of first transistor with control signal being in accordance with first clock, wherein when first transistor is de-activated, capacitor boosts voltage of first node to first voltage by voltage being applied to or end of capacitor, voltage applied to or end being at least ½ as great as first supply voltage, and control signal generating circuit sets voltage of control signal when first transistor is de-activated to be first voltage of first node, and sets voltage of control signal when first transistor is activated to be voltage, difference between voltage and first voltage being equal to or smaller than value of first supply voltage.Type: ApplicationFiled: May 10, 2010Publication date: December 2, 2010Applicants: NEC ELECTRONICS CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yoshihiro NAGAI, Masakazu AMANAI, Masahiko KASHIMURA, Masato TAKI, Norihiro HONDA, Kazushi YAMANAKA
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Publication number: 20100124125Abstract: A nonvolatile memory device includes a memory cell that stores data by presence or absence of electrons accumulated in a floating gate, a read reference current generator that generates a read reference current for reading data from the memory cell based on a constant current from a constant current generator included therein, and a read voltage generator that generates a read voltage to be applied to a control gate of the memory cell during data reading. The read reference current generator generates a monitor voltage that varies according to variation of the read reference current and a threshold voltage of the memory cell. The read voltage generator generates the read voltage based on the monitor voltage.Type: ApplicationFiled: November 17, 2009Publication date: May 20, 2010Applicants: NEC ELECTRONICS CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masakazu AMANAI, Masahiko KASHIMURA, Yoshihiro NAGAI, Masato TAKI, Norihiro HONDA, Kazushi YAMANAKA
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Patent number: 4887845Abstract: A label includes a label body which is a conventional one that can be mass-produced in advance and a photograph which is bonded to the label body or inserted into a cut portion provided in the label body. At least the obverse surface of the combination of the label body and the photograph is covered with a substantially transparent film.Type: GrantFiled: March 13, 1987Date of Patent: December 19, 1989Assignee: Tokyo Nagai Co., Ltd.Inventor: Yoshihiro Nagai