Abstract: A non-volatile semiconductor memory includes a plurality of memory cells and a driver for selectively driving the memory cells. The driver includes a first drive portion and a second drive portion. The first drive portion is provided for applying a source voltage higher than a power source voltage to a source region of the memory cell. The second drive portion is provided for applying a specific low voltage to a drain region of the memory cell for writing data having a first logic level, so that a writing current flows in the memory cell. Further, the second drive portion is provided for applying a specific high voltage higher than the power source voltage as a writing prohibition voltage to a drain region of the memory cell for writing data having a second logic level, so that the writing current is prevented from flowing in the memory cell.

Abstract: In a current drive circuit, variation in output current is reduced. A current adjustment section and a current output section generate a grayscale according to a target grayscale. The current adjustment section generates an intermediate current lint, which is a reference current Iref multiplied by a first coefficient, and the current output section generates an output current Iout, which is the intermediate current Iint multiplied by a second coefficient. The minimum value of the first coefficient is set in advance such that when the first coefficient is at a minimum value the voltage at a node (for the minimum grayscale) is greater than or equal to a predetermined first value which is larger than the operation threshold voltage of PMOS transistors in the current output section.

Abstract: A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one of the internal test signal. The semiconductor integrated circuit further includes a current generator coupled to the delay time measurement terminal, and still further includes a plurality of delay time measurement transistors coupled to the delay time measurement terminal. The delay time measurement transistors have a plurality of control electrodes coupled to the logic circuit to receive the internal test signals. Alternatively, the semiconductor integrated circuit may include an input switching circuit coupled between the logic circuit and the CUT and a pseudo test terminal coupled to the CUT and the logic circuit.

Abstract: A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one of the internal test signal. The semiconductor integrated circuit further includes a current generator coupled to the delay time measurement terminal, and still further includes a plurality of delay time measurement transistors coupled to the delay time measurement terminal. The delay time measurement transistors have a plurality of control electrodes coupled to the logic circuit to receive the internal test signals. Alternatively, the semiconductor integrated circuit may include an input switching circuit coupled between the logic circuit and the CUT and a pseudo test terminal coupled to the CUT and the logic circuit.

Abstract: In a current drive circuit, variation in output current is reduced. A current adjustment section and a current output section generate a grayscale according to a target grayscale. The current adjustment section generates an intermediate current lint, which is a reference current Iref multiplied by a first coefficient, and the current output section generates an output current lout, which is the intermediate current lint multiplied by a second coefficient. The minimum value of the first coefficient is set in advance such that when the first coefficient is at a minimum value the voltage at a node (for the minimum grayscale) is greater than or equal to a predetermined first value which is larger than the operation threshold voltage of PMOS transistors in the current output section.

Abstract: A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one of the internal test signal. The semiconductor integrated circuit further includes a current generator coupled to the delay time measurement terminal, and still further includes a plurality of delay time measurement transistors coupled to the delay time measurement terminal. The delay time measurement transistors have a plurality of control electrodes coupled to the logic circuit to receive the internal test signals. Alternatively, the semiconductor integrated circuit may include an input switching circuit coupled between the logic circuit and the CUT and a pseudo test terminal coupled to the CUT and the logic circuit.

Abstract: A semiconductor integrated circuit, which operates in accordance with a power supply voltage and an external clock signal and includes a memory circuit, includes a control circuit, and first and second internal circuits. The control circuit controls the memory circuit in accordance with the power supply voltage. The first internal circuit generates an internal power supply voltage for the control circuit. The second internal circuit generates an internal clock signal for the control circuit. The semiconductor integrated circuit further includes first and second power-on reset circuits. The first power-on reset circuit generates a first power-on reset signal for the first internal circuit after the power supply voltage is generated. The second power-on reset circuit generates a second power-on reset signal for the control circuit. The second power-on reset signal is input to the control circuit after the internal clock signal is input to the control circuit.

Abstract: A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one of the internal test signal. The semiconductor integrated circuit further includes a current generator coupled to the delay time measurement terminal, and still further includes a plurality of delay time measurement transistors coupled to the delay time measurement terminal. The delay time measurement transistors have a plurality of control electrodes coupled to the logic circuit to receive the internal test signals. Alternatively, the semiconductor integrated circuit may include an input switching circuit coupled between the logic circuit and the CUT and a pseudo test terminal coupled to the CUT and the logic circuit.

Abstract: A semiconductor integrated circuit capable of accurately measuring a time lag difference in operation test wiring is disclosed. It is provided with nMOS transistors in which each control terminal is connected to a signal terminal of a memory macro. Since the nMOS transistors are turned off when the test signals TCLK, TWE, and TRE are all at a low level, the potential of a pad which is connected to a drain is pulled up by a current generator. When the signal TCLK is changed to a high level, the transistor is turned on and the potential of the pad is changed to a low level. Then, a time lag from the moment at which the signal TCLK is changed to a high level to the moment at which the pad is changed to a low level is measured.

Abstract: A semiconductor integrated circuit, which operates in accordance with a power supply voltage and an external clock signal and includes a memory circuit, includes a control circuit, and first and second internal circuits. The control circuit controls the memory circuit in accordance with the power supply voltage. The first internal circuit generates an internal power supply voltage for the control circuit. The second internal circuit generates an internal clock signal for the control circuit. The semiconductor integrated circuit further includes first and second power-on reset circuits. The first power-on reset circuit generates a first power-on reset signal for the first internal circuit after the power supply voltage is generated. The second power-on reset circuit generates a second power-on reset signal for the control circuit. The second power-on reset signal is input to the control circuit after the internal clock signal is input to the control circuit.

Abstract: A semiconductor integrated circuit, which operates in accordance with a power supply voltage and an external clock signal and includes a memory circuit, includes a control circuit, and first and second internal circuits. The control circuit controls the memory circuit in accordance with the power supply voltage. The first internal circuit generates an internal power supply voltage for the control circuit. The second internal circuit generates an internal clock signal for the control circuit. The semiconductor integrated circuit further includes first and second power-on reset circuits. The first power-on reset circuit generates a first power-on reset signal for the first internal circuit after the power supply voltage is generated. The second power-on reset circuit generates a second power-on reset signal for the control circuit. The second power-on reset signal is input to the control circuit after the internal clock signal is input to the control circuit.

Abstract: An arbiter circuit minimizes the occurrence of malfunctions and permits easy adjustment. The arbiter circuit includes a data transfer request signal holding device for accepting a plurality of data transfer request signals and holding the data transfer request signals in response to predetermined timing signals, a prioritizing device for determining only a signal with the highest priority at a certain point as a valid signal and the signals with lower priorities as invalid signals in order to assign priorities to output signals from the data transfer request signal holding device, and a delaying device for generating data transfer execution signals from the output signals of the prioritizing device. This arrangement restrains the occurrence of errors in assigning priorities to data transfer request signals and permits easy priority timing setting, thus allowing easy adjustment of a circuit to be achieved.

Abstract: A new and improved semiconductor memory that facilitates machining of iterated circuits and solves the problems of the prior art such as the lengthy machining process, the compromised machining accuracy and the considerable time required for device evaluation is provided. A semiconductor memory 10 is provided with a plurality of output circuits 11 and a fuse circuit 12 connected to each of the output circuits. The fuse circuit outputs output signals N1 and N2 to the individual output circuits, the signal levels of which are fixed to either H level or L level depending upon whether or not fuses f1 and f2 in the fuse circuit are disconnected. The output circuits are each provided with an output buffer circuit unit 112 and a pre-driver circuit unit 111 that drives the output buffer circuit unit. The driving capability of the pre-driver circuit unit is determined by the output signal from the fuse circuit.

Abstract: A voltage dropping power unit is provided which is capable of reducing power consumption in the voltage dropping power unit while a semiconductor memory device is placed in a quiescent state. The voltage dropping power unit is provided with a voltage control circuit to supply a dropped voltage controlled depending on a control voltage to the semiconductor memory device, a reference circuit to generate a reference voltage used to produce a control voltage and a differential circuit to make the dropped voltage equal to the reference voltage irrespective of a level of a voltage output from the voltage control circuit. The reference circuit has a voltage dividing resistor used to produce a reference voltage and a switching device used to form a short-circuit across the voltage dividing resistor.