Abstract: Digital data provided in the form of a serial signal is fetched into an N-bit shift register and parallel N-bit data output therefrom is provided as address data to address input terminals of a memory. In the memory there are prestored at respective addresses defined by the N-bit data the total sum value of multiplied outputs obtained by multiplying the address values and the bit data of a coefficient h(n-i) defining an impulse response characteristic. The N-bit data is provided to an address input terminal of the memory to read out therefrom a digital value corresponding to the output voltage of a digital filter. The digital value is D/A converted to obtain the output voltage of the digital filter.

Abstract: A phase difference signal generator responds to two input signals to generates two phase difference signals which rise at a time interval corresponding to the phase difference between the two input signals and fall at the same time. A lagging signal detector detects a lagging one of the two phase difference signals and a pulse generator responds to the detected output from the lagging signal detector to generate an appendage pulse of a width larger than a predetermined width. The appendage pulse is appended, by a pulse appending circuit, to each of the two phase difference signals to form an extend phase difference signal. A phase difference detector detects the difference between the two extended phase difference signals and outputs a low-frequency component of the difference as a voltage corresponding to the phase difference between the two input signals.