Patents by Inventor Yoshihiro Obara

Yoshihiro Obara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9177990
    Abstract: A method for forming an impurity layer, includes forming a resist material 16 on a surface portion of a semiconductor substrate 15; exposing the resist material using a grating mask 10 comprising a light transmission region 11 including a plurality of unit light transmission regions 14 being arranged two-dimensionally, each being composed of a plurality of minute partial sections 13A to 13D having different transmittance; forming a resist layer 18 on the surface of the semiconductor substrate 15 by developing the exposed resist material, the resist layer including a thin film region 17 having a film thickness corresponding to the transmittance of the light transmission region; implanting ions to the semiconductor substrate 15 via the thin film region; and diffusing ion groups 21A?, 21B?, 21C?, and 21D? that are implanted at the same depth such that the ion groups are coupled in a lateral direction.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: November 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ken Tomita, Yoshihiro Obara
  • Publication number: 20120077304
    Abstract: A method for forming an impurity layer, includes forming a resist material 16 on a surface portion of a semiconductor substrate 15; exposing the resist material using a grating mask 10 comprising a light transmission region 11 including a plurality of unit light transmission regions 14 being arranged two-dimensionally, each being composed of a plurality of minute partial sections 13A to 13D having different transmittance; forming a resist layer 18 on the surface of the semiconductor substrate 15 by developing the exposed resist material, the resist layer including a thin film region 17 having a film thickness corresponding to the transmittance of the light transmission region; implanting ions to the semiconductor substrate 15 via the thin film region; and diffusing ion groups 21A?, 21B?, 21C?, and 21D? that are implanted at the same depth such that the ion groups are coupled in a lateral direction.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 29, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ken TOMITA, Yoshihiro Obara
  • Patent number: 8004589
    Abstract: A signal charge transfer channel region includes a first polysilicon gate electrode as a storage electrode for storing signal charges and a second polysilicon gate electrode as a barrier electrode for transferring the signal charges stored under the first polysilicon gate electrode to under the first polysilicon gate electrode adjacent to the first polysilicon gate electrode. The both end portions of the plurality of first and second polysilicon gate electrodes are alternately arranged perpendicularly to a transfer direction of signal charges and central portions thereof are alternately arranged obliquely to a transfer direction of signal charges.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: August 23, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Obara
  • Publication number: 20080284893
    Abstract: A signal charge transfer channel region includes a first polysilicon gate electrode as a storage electrode for storing signal charges and a second polysilicon gate electrode as a barrier electrode for transferring the signal charges stored under the first polysilicon gate electrode to under the first polysilicon gate electrode adjacent to the first polysilicon gate electrode. The both end portions of the plurality of first and second polysilicon gate electrodes are alternately arranged perpendicularly to a transfer direction of signal charges and central portions thereof are alternately arranged obliquely to a transfer direction of signal charges.
    Type: Application
    Filed: May 16, 2008
    Publication date: November 20, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshihiro Obara
  • Patent number: 5523658
    Abstract: A deflection yoke device comprises a convergence correction circuit connected between a vertical deflection coil and correction coils. The convergence correction circuit includes a first, second and third impedance elements connected in parallel and at least two diodes. The diodes are connected in series in the same direction and respond to a vertical deflection current of the vertical deflection coil to regulate a current flowing through the correction coils to thereby correct the YH mis-convergence.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: June 4, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Kouji Fukuma, Nobutaka Okuyama, Soichi Sakurai, Hiroshi Yoshioka, Yoshihiro Obara, Takahisa Mizuta
  • Patent number: 5498939
    Abstract: A deflection yoke attached to a color cathode ray tube forming multiple electron beams arranged in line, and in particular a deflection yoke having convergence correction apparatus. Circuit components such as a plurality of resistors, variable resistors, and diodes are connected in parallel with vertical deflection coils. A part of a vertical deflection current flowing through the vertical deflection coils is diverted to the circuit components. Furthermore, the amount of the diverted current is made adjustable so that it will differ between a former part of a vertical deflection period and a latter part thereof. As a result, horizontal line misconvergence at upper and lower ends of the screen can be completely corrected.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: March 12, 1996
    Assignees: Hitachi, Ltd., Hitachi Mizusawa Electronics Co., Ltd.
    Inventors: Kooji Fukuma, Soichi Sakurai, Nobutaka Okuyama, Yoshio Satoh, Yoshihiro Obara
  • Patent number: 5017900
    Abstract: A deflection yoke is constructed of a truncated conical hollow core, a pair of saddle-shaped horizontal deflection coils disposed inside the core, and a pair of toroidal vertical deflection coils wound on the core or a pair of vertical deflection coils wound in a saddle-like configuration and arranged in the vicinity of the core. A pair of cancellation coils opposing each other on an imaginary axis which passes through a central axis of the core in the direction of vertical deflection are arranged near front end sections of the vertical deflection coils, respectively. A central axis of each of said cancellation coils is inclined at a predetermined angle relative to the central axis of the core. The cancellation coils are connected with the horizontal deflection coils, respectively.
    Type: Grant
    Filed: February 9, 1990
    Date of Patent: May 21, 1991
    Assignee: Hitachi Mizusawa Electronics Co., Ltd.
    Inventors: Mitugu Ura, Yoshihiro Obara, Kazushi Takahashi