Abstract: It is an object of the present invention to provide an improved method of manufacturing a self-emission unit including a self-emission module having self-emission elements formed on a substrate, and a frame for protecting the self-emission modules, without carrying out some troublesome steps, thus making it possible to manufacture the self-emission unit in a shortened time. Another object of the present invention is to provide an improved self-emission unit capable of being attached to an attachment base with a high precision. The self-emission unit has a self-emission module and a frame. The frame is provided to cover a part or the whole of the self-emission module so as to protect the same. Further, the frame has fastening sections for attaching the self-emission module to an attachment base. The frame is formed integrally with the self-emission module so that it is possible to avoid some troublesome steps and thus shorten manufacturing time.

Abstract: It is an object of the present invention to provide an improved method of manufacturing a self-emission unit including a self-emission module having self-emission elements formed on a substrate, and a frame for protecting the self-emission modules, without carrying out some troublesome steps, thus making it possible to manufacture the self-emission unit in a shortened time. Another object of the present invention is to provide an improved self-emission unit capable of being attached to an attachment base with a high precision. The self-emission unit has a self-emission module and a frame. The frame is provided to cover a part or the whole of the self-emission module so as to protect the same. Further, the frame has fastening sections for attaching the self-emission module to an attachment base. The frame is formed integrally with the self-emission module so that it is possible to avoid some troublesome steps and thus shorten manufacturing time.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208t) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208t) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208t) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208t) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208f) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208f) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208f) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208f) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208f) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208f) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: An organic electroluminescent display device includes an organic electroluminescent element formed on a substrate thereof and having an organic compound layer group sandwiched between cathodes and anodes. The organic compound layer group has laminated electroluminescence functional layers formed of at least one kind of organic compound. Further, the organic electroluminescent display device includes an airtight case that encloses the organic electroluminescent element with a space formed between the airtight case itself and the organic electroluminescent element and isolates the organic electroluminescent element from outside air, and a filler gas filling the space within the airtight case. The filler gas contains at least one kind of combustion supporting gas.

Abstract: A dynamic RAM in which a groove (20) is formed on the main surface of a semiconductor substrate; a highly concentrated semiconductor layer (80) having one conductive type is formed inside the groove (20) to a depth sufficient to contain the first and second impurity diffusion areas (53) and (22), which are formed on the top of this groove and have the opposite conductive type; a capacitor C.sub.1 formed inside the groove (20), while a transfer gate Tr.sub.1 is formed on the highly concentrated semiconductor layer (80); and the diffusion area (53) is used to connect them.

Abstract: A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film(54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell. Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.

Abstract: A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

Abstract: A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film (54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell.Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via substrate electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.

Abstract: A process is disclosed herein for increasing yield in a semiconductor circuity having redundant circuitry for replacing defective normal circuitry in the semiconductor integrated circuit. In the first step, an insufficient sinter operation (50) is carried out in a hydrogen atmosphere at a temperature of less than 350.degree. C. At this temperature, no significant change will be seen in the interface trap density. Thereafter, the integrated circuit is tested (54,56) and the defective normal circuitry then is replaced (58) with the redundant circuitry. The integrated circuit is then subjected to a sufficient sinter operation (64) which is an operation wherein the substrate is disposed at a temperature between 350.degree. C.-500.degree. C. for more than 30 minutes. This sufficient sinter operation is performed in a hydrogen atmosphere, allowing dangling bonds at the interface to be terminated with hydrogen. Preferable, the optimal temperature for the sufficient sinter is approximately 400.degree. C.

Abstract: An electro-luminescence device is described, which includes a laminate composed of a transparent substrate having successively laminated thereon a transparent electrode, a luminous layer, a dielectric layer, and a back electrode, with a back protective material being adhered to the back electrode through an adhesive resin film, wherein the back protective material is a moisture impermeable protective material and the adhesive resin film is a thermo-plastic resin film having a thickness of from 10 to 200 .mu.m, and a method for production thereof is also described.

Abstract: A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100).

Abstract: A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory/device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

Abstract: A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100). It is possible to form the element areas according to designs, and it is also possible to flatten the surface without wire cutting in the conductive layer.

Abstract: Substrate bias generating circuit for MIS semiconductor device comprising an oscillating circuit, a capacitor, an MOS transistor and a Schottky barrier diode. One end of the oscillating circuit is connected to a V.sub.ss terminal which provides a reference potential. The capacitor is connected at one end thereof to the other end of the oscillating circuit. The MOS transistor is connected between the V.sub.ss terminal and the other end of the capacitor, with the Schottky barrier diode being connected between a node located between the other end of the capacitor and the MOS transistor, and the substrate. The Schottky barrier diode is operated by the majority carrier, thereby enabling the majority charge to be directly pumped out of the substrate and into the terminal V.sub.ss through the Schottky barrier diode with stability without requiring an injection of the minority charge into the semiconductor substrate.

Abstract: An image developing device for use in an electrophotographic copying apparatus or a printer includes a developing roller for supplying toner to a latent image formed on a latent image carrier to develop the latent image into a visible toner image. The image developing device also includes a toner supply roller independently rotatable in abutting engagement with the developing roller for supplying the toner onto the developing roller. Each of the toner supply roller and the developing roller is electrically conductive. An electric potential with its polarity dependent on whether the toner is positively or negatively chargeable is applied between the toner supply toner and the developing roller by a bias voltage distributing circuit.

Abstract: A developing device includes a developing sleeve driven to rotate for transporting a film of charged developer as carried thereon past a developing station where the film of developer is applied to an electrostatic latent image to have it developed. Also provided is a sponge roller pressed against and driven to rotate in the same rotating direction as that of the developing sleeve, so that the developer is supplied to the developing sleeve at one side of the contact between the developing sleeve and the sponge roller and any residual developer on the developing sleeve is removed at the other side of the contact. Preferably, a desired voltage difference is established between the developing sleeve and the sponge roller. Furthermore, the sponge roller is preferably so structured to have a sufficient conductivity level at least at its outer peripheral surface thereby allowing the residual charge on the developing sleeve to be discharged sufficiently.