Patents by Inventor Yoshihiro Ohkura

Yoshihiro Ohkura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8224062
    Abstract: An individually isolated wafer adapted to a semiconductor chip is subjected to inspection in which an infrared ray is irradiated onto the backside of the wafer whose surface is sealed with a resin layer such that the optical axis thereof perpendicularly or slantingly crosses the surface of the wafer, whereby an image clearly showing cracks formed in the wafer is produced based on the reflected ray. Before or after an exterior inspection process, a tape inspection process is performed by use of an image of the surface of a dicing tape, in which a plurality of semiconductor chips are once attached onto and then separated from, so as to detect at least one of a defective element, a crack mark, and a foreign mark with regard to the semiconductor chip subjected to inspection.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: July 17, 2012
    Assignee: Yamaha Corporation
    Inventors: Yoshihiro Ohkura, Yoshio Fukuda
  • Patent number: 7830011
    Abstract: A semiconductor device, encapsulated in a wafer level chip size package (WLCSP), includes a plurality of pad electrodes formed on the surface of a semiconductor chip, wherein a first insulating layer is formed on the surface of the semiconductor chip except the pad electrodes; a plurality of connection electrodes and at least one heat-dissipation electrode are formed on the surface of the first insulating layer; the pad electrodes and the connection electrodes are mutually connected via a first wiring portion; the heat-dissipation electrode is connected with a second wiring portion; and a second insulating layer is formed to enclose the electrodes and wiring portions, wherein the second wiring portion is arranged in proximity to a heating portion of the semiconductor chip and is formed on the surface of the first insulating layer except the prescribed region corresponding to the first wiring portion.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: November 9, 2010
    Assignee: Yamaha Corporation
    Inventors: Kentaro Nomoto, Yuki Igawa, Hiroshi Saitoh, Takashi Sato, Toshio Ohashi, Yoshihiro Ohkura
  • Patent number: 7642799
    Abstract: A test chip socket comprises a contact block fixed to a tester substrate, a tray mounted to the contact block, the tray having a convex part for positioning test target chips to a plurality of mount positions, and a plurality of probes each of which is held by the contact block and contacts the tester substrate and the test target chip, wherein each probe contacts with a terminal of each test target chip mounted to the mounting position when the tray mounting the plurality of the test target chip is fixed to the contact block.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: January 5, 2010
    Assignee: Yamaha Corporation
    Inventor: Yoshihiro Ohkura
  • Patent number: 7626410
    Abstract: An apparatus for testing a semiconductor device that has opposing first and second sides is provided. The semiconductor device includes at least one functional unit on the first side and a plurality of terminals on the second side. The apparatus may include, but is not limited to, a mounting structure, and a plurality of electrodes. The mounting structure has at least one stage that is configured to allow the semiconductor device to be mounted thereon. The mounting structure has a communicating hole that penetrates the mounting structure from the stage. The communicating hole allows the at least one functional unit to face to the communicating hole while the semiconductor device is mounted on the stage. Each of the plurality of electrodes is configured to be contactable to a corresponding one of the plurality of terminals, while the semiconductor device is mounted on the stage.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: December 1, 2009
    Assignee: Yamaha Corporation
    Inventor: Yoshihiro Ohkura
  • Patent number: 7388198
    Abstract: An electron microscope capable of producing EELS (electron energy-loss spectroscopy) has a spectral position correcting signal supply circuit for supplying a spectral position correcting signal H to a first driver amplifier to project spectra at the center of a CCD camera. This correcting signal H corresponds to a beam deflection signal A? supplied from a scan generator to a second driver amplifier, an excitation signal B? supplied from an intermediate lens excitation signal supply circuit to a third driver amplifier, and another excitation signal supplied from a projector lens excitation signal supply circuit to a fourth driver amplifier.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: June 17, 2008
    Assignee: Jeol Ltd.
    Inventor: Yoshihiro Ohkura
  • Publication number: 20080094094
    Abstract: An apparatus for testing a semiconductor device that has opposing first and second sides is provided. The semiconductor device includes at least one functional unit on the first side and a plurality of terminals on the second side. The apparatus may include, but is not limited to, a mounting structure, and a plurality of electrodes. The mounting structure has at least one stage that is configured to allow the semiconductor device to be mounted thereon. The mounting structure has a communicating hole that penetrates the mounting structure from the stage. The communicating hole allows the at least one functional unit to face to the communicating hole while the semiconductor device is mounted on the stage. Each of the plurality of electrodes is configured to be contactable to a corresponding one of the plurality of terminals, while the semiconductor device is mounted on the stage.
    Type: Application
    Filed: September 24, 2007
    Publication date: April 24, 2008
    Applicant: YAMAHA CORPORATION
    Inventor: YOSHIHIRO OHKURA
  • Publication number: 20080054925
    Abstract: A test chip socket comprises a contact block fixed to a tester substrate, a tray mounted to the contact block, the tray having a convex part for positioning test target chips to a plurality of mount positions, and a plurality of probes each of which is held by the contact block and contacts the tester substrate and the test target chip, wherein each probe contacts with a terminal of each test target chip mounted to the mounting position when the tray mounting the plurality of the test target chip is fixed to the contact block.
    Type: Application
    Filed: August 20, 2007
    Publication date: March 6, 2008
    Applicant: YAMAHA CORPORATION
    Inventor: YOSHIHIRO Ohkura
  • Publication number: 20080037859
    Abstract: An individually isolated wafer adapted to a semiconductor chip is subjected to inspection in which an infrared ray is irradiated onto the backside of the wafer whose surface is sealed with a resin layer such that the optical axis thereof perpendicularly or slantingly crosses the surface of the wafer, whereby an image clearly showing cracks formed in lie wafer is produced based on the reflected ray.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 14, 2008
    Applicant: YAMAHA CORPORATION
    Inventors: YOSHIHIRO OHKURA, YOSHIO FUKUDA
  • Patent number: 7262512
    Abstract: A surface mount chip package comprises a package housing made of a prescribed resin, which is formed to cover a semiconductor chip while avoiding a plurality of conductors extending from the semiconductor chip. A plurality of solder balls are arranged in the package housing in correspondence with a main surface of the semiconductor chip having an integrated circuit and are interconnected with the conductors respectively. An index serving as a marking member is arranged together with the solder balls so as to bring a directivity realized by the shape thereof when viewed in the thickness direction of the semiconductor chip. This allows a user to easily recognize the inclination and position of the package housing without using the solder balls in view of the index, thus establishing a prescribed positioning for an electrical test such as a probing test.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: August 28, 2007
    Assignee: Yamaha Corporation
    Inventor: Yoshihiro Ohkura
  • Patent number: 7230326
    Abstract: A semiconductor device incorporated in a wire bonding chip size package (WBCSP) is designed such that a plurality of pads are formed on the surface of a semiconductor substrate and are connected to external terminals via conductive posts, wherein first and second rewiring patterns are respectively connected to the pads. All elements are sealed within an insulating layer such that the external terminals are partially exposed on the surface, wherein an uppermost portion of a conductive wire is positioned above the rewiring patterns and is also positioned below the lower ends of the external terminals. This realizes short wiring distances between the pads and the external terminals; hence, it is possible to reduce the wiring resistance and wiring delay time; it is possible to increase a freedom of degree regarding wiring without causing short-circuit failure; and, it is possible to easily change the wiring in a short period of time.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: June 12, 2007
    Assignee: Yamaha Corporation
    Inventor: Yoshihiro Ohkura
  • Publication number: 20060049507
    Abstract: A semiconductor device incorporated in a wire bonding chip size package (WBCSP) is designed such that a plurality of pads are formed on the surface of a semiconductor substrate and are connected to external terminals via conductive posts, wherein first and second rewiring patterns are respectively connected to the pads. All elements are sealed within an insulating layer such that the external terminals are partially exposed on the surface, wherein an uppermost portion of a conductive wire is positioned above the rewiring patterns and is also positioned below the lower ends of the external terminals. This realizes short wiring distances between the pads and the external terminals; hence, it is possible to reduce the wiring resistance and wiring delay time; it is possible to increase a freedom of degree regarding wiring without causing short-circuit failure; and, it is possible to easily change the wiring in a short period of time.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 9, 2006
    Inventor: Yoshihiro Ohkura
  • Publication number: 20060022137
    Abstract: An electron microscope capable of producing EELS (electron energy-loss spectroscopy) has a spectral position correcting signal supply circuit for supplying a spectral position correcting signal H to a first driver amplifier to project spectra at the center of a CCD camera This correcting signal H corresponds to a beam deflection signal A? supplied from a scan generator to a second driver amplifier, an excitation signal B? supplied from an intermediate lens excitation signal supply circuit to a third driver amplifier, and another excitation signal supplied from a projector lens excitation signal supply circuit to a fourth driver amplifier.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 2, 2006
    Applicant: JEOL Ltd.
    Inventor: Yoshihiro Ohkura
  • Publication number: 20050199995
    Abstract: A semiconductor device, encapsulated in a wafer level chip size package (WLCSP), includes a plurality of pad electrodes formed on the surface of a semiconductor chip, wherein a first insulating layer is formed on the surface of the semiconductor chip except the pad electrodes; a plurality of connection electrodes and at least one heat-dissipation electrode are formed on the surface of the first insulating layer; the pad electrodes and the connection electrodes are mutually connected via a first wiring portion; the heat-dissipation electrode is connected with a second wiring portion; and a second insulating layer is formed to enclose the electrodes and wiring portions, wherein the second wiring portion is arranged in proximity to a heating portion of the semiconductor chip and is formed on the surface of the first insulating layer except the prescribed region corresponding to the first wiring portion.
    Type: Application
    Filed: March 10, 2005
    Publication date: September 15, 2005
    Inventors: Kentaro Nomoto, Yuki Igawa, Hiroshi Saitoh, Takashi Sato, Toshio Ohashi, Yoshihiro Ohkura
  • Patent number: 6800853
    Abstract: In the electron microscope in accordance with the present invention, the electron beam is scanned during a SEARCH mode for searching for a field of view of interest to obtain a TEM image. The state of excitation of the condenser lens does not vary when the mode of operation is switched from the SEARCH mode to a PHOTO mode.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: October 5, 2004
    Assignee: Jeol Ltd.
    Inventor: Yoshihiro Ohkura
  • Publication number: 20040124514
    Abstract: A surface mount chip package comprises a package housing made of a prescribed resin, which is formed to cover a semiconductor chip while avoiding a plurality of conductors extending from the semiconductor chip. A plurality of solder balls are arranged in the package housing in correspondence with a main surface of the semiconductor chip having an integrated circuit and are interconnected with the conductors respectively. An index serving as a marking member is arranged together with the solder balls so as to bring a directivity realized by the shape thereof when viewed in the thickness direction of the semiconductor chip. This allows a user to easily recognize the inclination and position of the package housing without using the solder balls in view of the index, thus establishing a prescribed positioning for an electrical test such as a probing test.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 1, 2004
    Inventor: Yoshihiro Ohkura
  • Patent number: 6621176
    Abstract: An input device for use in a vehicle for inputting settings pertaining to a driver's intention of acceleration and deceleration includes a running mode selection switch and an acceleration/deceleration switch. A plurality of modes, for example, a manual speed change mode, an automatic speed change mode, a speed setting mode, and a distance-between-cars setting mode, are selectively set in the running mode selection switch. The acceleration/deceleration switch allows an accelerating or decelerating operation in correspondence to the selected mode. Operation switches which have been conventionally provided separately for each of functions are integrated into two parts, that is, the running mode selection switch and the acceleration/deceleration switch. After a desired mode has been selected, a desired function can be realized only by operation corresponding to a driver's intention of acceleration or deceleration.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: September 16, 2003
    Assignee: Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho
    Inventors: Chikao Nagasaka, Yoshihiro Ohkura, Hiroshi Tsuge, Toru Nakamura
  • Publication number: 20020100873
    Abstract: In the electron microscope in accordance with the present invention, the electron beam is scanned during a SEARCH mode for searching for a field of view of interest to obtain a TEM image. The state of excitation of the condenser lens does not vary when the mode of operation is switched from the SEARCH mode to a PHOTO mode.
    Type: Application
    Filed: November 16, 2001
    Publication date: August 1, 2002
    Applicant: JEOL Ltd.
    Inventor: Yoshihiro Ohkura