Patents by Inventor Yoshihiro Oikawa
Yoshihiro Oikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10360144Abstract: A storage apparatus includes a non-volatile memory and a controller to determine whether or not to compress data at a time when a non-volatile memory device receives the data from a host apparatus. A storage controller transmits a specified logical address range, an update frequency level of the specified logical address range, and specified data to a device controller. The update frequency level may indicate whether data is Hot or Cold. On the basis of the update frequency level of the specified logical address range, the device controller determines whether to compress the specified data. When a determination is made to compress the specified data, the device controller compresses the specified data to generate compressed data, and writes the compressed data into a non-volatile memory which may be a flash memory device. A degradation rank of physical blocks in the flash memory may include at least Young and Old.Type: GrantFiled: February 27, 2015Date of Patent: July 23, 2019Assignee: HITACHI, LTD.Inventors: Masatsugu Oshimi, Yoshihiro Oikawa, Hiroshi Hirayama, Junji Ogawa
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Patent number: 10310770Abstract: This nonvolatile memory device has a blockwise-erase nonvolatile memory including a plurality of physical areas, and also has a memory controller which transmits one of a plurality of types of commands to the nonvolatile memory. After an erase command to erase one of the physical areas has been transmitted, but before a response to that erase command is received, the memory controller determines whether to suspend the ongoing erasure of the physical area, on the basis of whether there is a command to be transmitted and/or on the basis of the degree of deterioration of the physical area being erased. If the determination is affirmative, the memory controller transmits a command to the nonvolatile memory to suspend the erasure.Type: GrantFiled: November 5, 2015Date of Patent: June 4, 2019Assignee: HITACHI, LTD.Inventors: Masatsugu Oshimi, Junji Ogawa, Yoshihiro Oikawa
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Patent number: 10198318Abstract: A nonvolatile memory device includes: a nonvolatile memory including a plurality of physical blocks; and a memory controller configured to execute an internal process of migrating data between physical blocks. The memory controller is configured to select, based on an update frequency level which is identified with respect to a logical address range from a higher-level apparatus, a physical block to be allocated to the logical address range from among the plurality of physical blocks. The memory controller is configured to determine, in the internal process, whether to set a migration destination level (an update frequency level of a migration destination physical block) to a same level as or a different level from a migration source level (an update frequency level of a migration source physical block) based on whether or not an attribute of the migration source physical block satisfies a prescribed condition.Type: GrantFiled: October 27, 2014Date of Patent: February 5, 2019Assignee: HITACHI, LTD.Inventors: Yoshihiro Oikawa, Hiroshi Hirayama, Kenta Ninose
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Publication number: 20180196622Abstract: This nonvolatile memory device has a blockwise-erase nonvolatile memory including a plurality of physical areas, and also has a memory controller which transmits one of a plurality of types of commands to the nonvolatile memory. After an erase command to erase one of the physical areas has been transmitted, but before a response to that erase command is received, the memory controller determines whether to suspend the ongoing erasure of the physical area, on the basis of whether there is a command to be transmitted and/or on the basis of the degree of deterioration of the physical area being erased. If the determination is affirmative, the memory controller transmits a command to the nonvolatile memory to suspend the erasure.Type: ApplicationFiled: November 5, 2015Publication date: July 12, 2018Inventors: Masatsugu OSHIMI, Junji OGAWA, Yoshihiro OIKAWA
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Patent number: 9898201Abstract: A non-volatile memory device includes a non-volatile memory and a memory controller which executes read from the non-volatile memory using a read option. The non-volatile memory includes a plurality of memory area units (e.g. dies described below), and each memory area unit includes a plurality of memory areas (e.g. pages). The memory controller holds management information in which a read option is recorded per memory area unit which is a unit larger than a memory area which is a read unit. The memory controller specifies a memory area unit including a read source memory area, selects a read option matching the specified memory area unit, and executes read from the read source memory area using the selected read option.Type: GrantFiled: March 24, 2014Date of Patent: February 20, 2018Assignee: Hitachi, Ltd.Inventors: Yoshihiro Oikawa, Hiroshi Hirayama
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Publication number: 20170351602Abstract: To determine whether or not to data is compressed at a timing when a non-volatile memory device receives the data from a host apparatus. A storage controller transmits a specified logical address range, an update frequency level of the specified logical address range, and specified data to a device controller. On the basis of the update frequency level of the specified logical address range, the device controller determines whether the specified data is compressed or not. When determination is made that the specified data is compressed, the device controller compresses the specified data to generate compressed data, and writes the compressed data into a non-volatile memory. When determination is made that the specified data is not compressed, the device controller writes the specified data into the non-volatile memory.Type: ApplicationFiled: February 27, 2015Publication date: December 7, 2017Applicant: HITACHI, LTD.Inventors: Masatsugu OSHIMI, Yoshihiro OIKAWA, Hiroshi HIRAYAMA, Junji OGAWA
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Publication number: 20170308722Abstract: A nonvolatile memory device includes: a nonvolatile memory including a plurality of physical blocks; and a memory controller configured to execute an internal process of migrating data between physical blocks. The memory controller is configured to select, based on an update frequency level which is identified with respect to a logical address range from a higher-level apparatus, a physical block to be allocated to the logical address range from among the plurality of physical blocks. The memory controller is configured to determine, in the internal process, whether to set a migration destination level (an update frequency level of a migration destination physical block) to a same level as or a different level from a migration source level (an update frequency level of a migration source physical block) based on whether or not an attribute of the migration source physical block satisfies a prescribed condition.Type: ApplicationFiled: October 27, 2014Publication date: October 26, 2017Inventors: Yoshihiro OIKAWA, Hiroshi HIRAYAMA, Kenta NINOSE
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Publication number: 20170075574Abstract: A non-volatile memory device includes a non-volatile memory and a memory controller which executes read from the non-volatile memory using a read option. The non-volatile memory includes a plurality of memory area units (e.g. dies described below), and each memory area unit includes a plurality of memory areas (e.g. pages). The memory controller holds management information in which a read option is recorded per memory area unit which is a unit larger than a memory area which is a read unit. The memory controller specifies a memory area unit including a read source memory area, selects a read option matching the specified memory area unit, and executes read from the read source memory area using the selected read option.Type: ApplicationFiled: March 24, 2014Publication date: March 16, 2017Applicant: HITACHI, LTD.Inventors: Yoshihiro OIKAWA, Hiroshi HIRAYAMA
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Patent number: 8843680Abstract: Each communication path between controllers and a plurality of storage devices has a plurality of expanders coupled in series. In order to shorten the time during which the communication path is not used for I/O, either (A) the length of time for which I/O suppression is set for the communication path is shortened, or (B) the overall time it takes for processing other than I/O processing is shortened. In the (A), a determination as to whether or not the coupling between the expanders has been disconnected is made for the I/O-suppressed communication path, and in a case where the result of this determination is negative, a discover process is carried out after releasing the I/O suppression with respect to this communication path. In the (B), the number of command issue times of updating routing control information of the expander is reduced.Type: GrantFiled: May 10, 2013Date of Patent: September 23, 2014Assignee: Hitachi, Ltd.Inventors: Yoshifumi Mimata, Yoshihiro Oikawa
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Patent number: 8725936Abstract: A storage system has: one or more flash memory chips, each of which has a storage region configured by a plurality of blocks; and a device controller that controls access to data corresponding to the storage regions of the flash memory chips. The device controller manages for each of the blocks the number of determination readings for determining read disturb on the basis of a read request with respect to data of each block from a higher-level device, and, when there is a block for which the number of determination readings becomes equal to or larger than a threshold represented as a standard indicating a predetermined state related to read disturb, transmits, to the higher-level device, notification information that includes information indicating that read disturb of the block enters the predetermined state.Type: GrantFiled: March 30, 2012Date of Patent: May 13, 2014Assignee: Hitachi, Ltd.Inventors: Yoshihiro Oikawa, Akifumi Suzuki, Taichi Yotsumoto
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Publication number: 20130262749Abstract: A storage system has: one or more flash memory chips, each of which has a storage region configured by a plurality of blocks; and a device controller that controls access to data corresponding to the storage regions of the flash memory chips. The device controller manages for each of the blocks the number of determination readings for determining read disturb on the basis of a read request with respect to data of each block from a higher-level device, and, when there is a block for which the number of determination readings becomes equal to or larger than a threshold represented as a standard indicating a predetermined state related to read disturb, transmits, to the higher-level device, notification information that includes information indicating that read disturb of the block enters the predetermined state.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Inventors: Yoshihiro Oikawa, Akifumi Suzuki, Taichi Yotsumoto
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Publication number: 20130254429Abstract: Each communication path between controllers and a plurality of storage devices has a plurality of expanders coupled in series. In order to shorten the time during which the communication path is not used for I/O, either (A) the length of time for which I/O suppression is set for the communication path is shortened, or (B) the overall time it takes for processing other than I/O processing is shortened. In the (A), a determination as to whether or not the coupling between the expanders has been disconnected is made for the I/O-suppressed communication path, and in a case where the result of this determination is negative, a discover process is carried out after releasing the I/O suppression with respect to this communication path. In the (B), the number of command issue times of updating routing control information of the expander is reduced.Type: ApplicationFiled: May 10, 2013Publication date: September 26, 2013Applicant: HITACHI, LTD.Inventors: Yoshifumi MIMATA, Yoshihiro OIKAWA
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Publication number: 20130246686Abstract: A higher-level system of a nonvolatile semiconductor storage device (hereinafter, semiconductor device) displays a GUI (Graphical User Interface), which receives a parameter group (one or more parameters) for controlling the processing of the semiconductor device. The higher-level system stores at least one of the parameters of the parameter group inputted to the GUI, and sends a command comprising the parameter group to the semiconductor device. The semiconductor device stores at least one of the parameters of the parameter group included in this command. The higher-level system and the semiconductor device each execute processing in accordance with the stored parameter. The semiconductor device sends, to the higher-level system, information of a log related to the processing executed in accordance with the stored parameter. The higher-level system displays feedback information on the basis of multiple times of logs. A user can change a desired parameter on the basis of this feedback information.Type: ApplicationFiled: March 19, 2012Publication date: September 19, 2013Inventors: Yoshiyuki Noborikawa, Yoshihiro Oikawa
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Patent number: 8527981Abstract: A storage device includes a plurality of expanders connected to a disk device and a controller unit for controlling the expanders. The disk device stores data transmitted from a host device. The controller determines whether, when download data is received from a predetermined terminal to update firmware of an expander, it is necessary to initialize a corresponding expander after downloading the download data by the expander, transmits determined initialization determining information determined to the terminal, transmits the download data to the corresponding expander, and instructs the corresponding expander to update the firmware at a timing for updating the firmware, which is determined by the terminal based on the initialization determining information.Type: GrantFiled: October 23, 2008Date of Patent: September 3, 2013Assignee: Hitachi, Ltd.Inventors: Yoshihiro Oikawa, Akio Nakajima, Ikuya Yagisawa
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Patent number: 8463949Abstract: Each communication path between controllers and a plurality of storage devices has a plurality of expanders coupled in series. In order to shorten the time during which the communication path is not used for I/O, either (A) the length of time for which I/O suppression is set for the communication path is shortened, or (B) the overall time it takes for processing other than I/O processing is shortened. In the (A), a determination as to whether or not the coupling between the expanders has been disconnected is made for the I/O-suppressed communication path, and in a case where the result of this determination is negative, a discover process is carried out after releasing the I/O suppression with respect to this communication path. In the (B), the number of command issue times of updating routing control information of the expander is reduced.Type: GrantFiled: June 2, 2010Date of Patent: June 11, 2013Assignee: Hitachi, Ltd.Inventors: Yoshifumi Mimata, Yoshihiro Oikawa
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Patent number: 8312312Abstract: A controller transmits a second protocol command to a target from among one or more switch devices. The second protocol command is a command which conforms to a second protocol type in which a connection established for transmitting a command to the target is broken during processing of the command by the target, and is defined as a command corresponding to a first protocol command, which is a command conforming to a first protocol type in which the connection remains established during processing of the command by the target.Type: GrantFiled: February 3, 2011Date of Patent: November 13, 2012Assignee: Hitachi, Ltd.Inventors: Yoshihiro Oikawa, Ikuya Yagisawa, Bunitsu Ando
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Publication number: 20110302368Abstract: Each communication path between controllers and a plurality of storage devices has a plurality of expanders coupled in series. In order to shorten the time during which the communication path is not used for I/O, either (A) the length of time for which I/O suppression is set for the communication path is shortened, or (B) the overall time it takes for processing other than I/O processing is shortened. In the (A), a determination as to whether or not the coupling between the expanders has been disconnected is made for the I/O-suppressed communication path, and in a case where the result of this determination is negative, a discover process is carried out after releasing the I/O suppression with respect to this communication path. In the (B), the number of command issue times of updating routing control information of the expander is reduced.Type: ApplicationFiled: June 2, 2010Publication date: December 8, 2011Applicant: HITACHI, LTD.Inventors: Yoshifumi Mimata, Yoshihiro Oikawa
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Publication number: 20110125943Abstract: A controller transmits a second protocol command to a target from among one or more switch devices. The second protocol command is a command which conforms to a second protocol type in which a connection established for transmitting a command to the target is broken during processing of the command by the target, and is defined as a command corresponding to a first protocol command, which is a command conforming to a first protocol type in which the connection remains established during processing of the command by the target.Type: ApplicationFiled: February 3, 2011Publication date: May 26, 2011Applicant: HITACHI, LTD.Inventors: Yoshihiro OIKAWA, Ikuya YAGISAWA, Bunitsu ANDO
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Patent number: 7904744Abstract: A controller transmits a second protocol command to a target from among one or more switch devices. The second protocol command is a command which conforms to a second protocol type in which a connection established for transmitting a command to the target is broken during processing of the command by the target, and is defined as a command corresponding to a first protocol command, which is a command conforming to a first protocol type in which the connection remains established during processing of the command by the target.Type: GrantFiled: January 14, 2008Date of Patent: March 8, 2011Assignee: Hitachi, Ltd.Inventors: Yoshihiro Oikawa, Ikuya Yagisawa, Bunitsu Ando
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Publication number: 20100058322Abstract: Provided is a storage device which can increase the speed of transmission/reception of data and reliability thereof.Type: ApplicationFiled: October 23, 2008Publication date: March 4, 2010Inventors: Yoshihiro Oikawa, Akio Nakajima, Ikuya Yagisawa