Abstract: A semiconductor device having a large on-state current and high reliability is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor over the second insulator. The fifth oxide is in contact with a top surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M, and Zn. The first oxide and the fifth oxide each contain at least one of constituent elements included in the second oxide. The third oxide and the fourth oxide each contain the element M.

Abstract: Provided is an aqueous coating composition capable of forming a fluororesin coating film layer with excellent electrical properties and surface physical properties, and good adhesive properties. A coating composition containing 2 or more kinds of fluororesins, wherein at least 1 kind of the fluororesin, a fluororesin (I), has a number of functional groups of 30 to 1,000 per 106 main-chain carbon atoms, and the coating composition further contains an inorganic filler, a surfactant, a liquid medium, and a non-fluororesin.

Abstract: Provided is an aqueous coating composition capable of forming a fluororesin coating film layer with excellent electrical properties and surface physical properties, and good adhesive properties. A coating composition containing 2 or more kinds of fluororesins, where at least 1 kind of the fluororesin, a fluororesin (I), has a number of functional groups of 30 to 1,000 per 106 main-chain carbon atoms, and where the coating composition further contains an inorganic filler, a surfactant, and a liquid medium.

Abstract: A lighting system includes a luminaire, a main controller that wirelessly transmits a command to control a dimming state to the luminaire at predetermined intervals, and an auxiliary controller that includes an operation switch and wirelessly transmits a start signal and an end signal of a press-and-hold action to the main controller when the press-and-hold action is performed on the operation switch.

Abstract: This invention provides a data processing device capable of operating a plurality of processing modules in parallel. Processes following a processing flow are assigned to the plural processing modules, respectively, and at least two of the processing modules are capable of running a same process. A network includes an arbitration circuit that, upon receiving a packet from a processing module, according to a process number attached to the packet, selects a processing module out of the processing modules capable of running the process, and outputs the packet to the selected processing module. This thus allows for autonomous transfer of a packet between each processing module and makes it possible to operate the processing modules in parallel.

Abstract: The thickness of an intermediate plate portion (31b) is smaller than the thickness of a stopper portion (31a). The thickness of a portion of a cylinder head gasket (20) having the stopper portion (31a) is set to be greater than the thickness of other portions of the cylinder head gasket (20). Before the cylinder head gasket (20) is provided between contact surfaces (12a, 13a), a space (S) is formed between the stopper portion (31a) and an adjustment stopper portion (32a), and the intermediate plate portion (31b) partially contacts the adjustment plate portion, and a bead (33a) contacts the adjustment plate portion (32b).

Abstract: This invention provides a data processing device capable of operating a plurality of processing modules in parallel. Processes following a processing flow are assigned to the plural processing modules, respectively, and at least two of the processing modules are capable of running a same process. A network includes an arbitration circuit that, upon receiving a packet from a processing module, according to a process number attached to the packet, selects a processing module out of the processing modules capable of running the process, and outputs the packet to the selected processing module. This thus allows for autonomous transfer of a packet between each processing module and makes it possible to operate the processing modules in parallel.

Abstract: A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.

Abstract: The thickness of an intermediate plate portion (31b) is smaller than the thickness of a stopper portion (31a). The thickness of a portion of a cylinder head gasket (20) having the stopper portion (31a) is set to be greater than the thickness of other portions of the cylinder head gasket (20). Before the cylinder head gasket (20) is provided between contact surfaces (12a, 13a), a space (S) is formed between the stopper portion (31a) and an adjustment stopper portion (32a), and the intermediate plate portion (31b) partially contacts the adjustment plate portion, and a bead (33a) contacts the adjustment plate portion (32b).

Abstract: A logic circuit optimizing apparatus for optimizing a designed logic circuit including a redundant circuit is disclosed. Conventionally, a large number of operations and limitations have been necessary in designing thereof, in order to detect faults included in the designed logic circuit, and the complete detection of the faults was impossible. The logic circuit optimizing apparatus, however, includes the steps of detecting a redundant circuit included in a designed logic circuit (55 to 59), and the step of deleting the detected redundant circuit (62) and, therefore, the redundant circuit can be completely removed from the designed logic circuit. A logic circuit without faults can be thus designed, and the complete detection of faults can be performed.

Abstract: An improved carpeting gate array having a plurality of basic cells (9) each comprising an N channel MOS transistor (8) and a P channel MOS transistor (7) continuously arranged in row and column directions comprises a logic cell region (20) comprising a plurality of basic cells (9) continuously formed in a channel width direction (a direction intersecting with a direction in which their gate electrodes (4) of a plurality of N channel or P channel MOS transistors are continuously arranged spaced apart from each other), and an interconnection region (21) for providing interconnections to the logic cells (20) continuously formed in the channel width direction. The size in a width direction of the interconnection region is defined by the size in a channel length direction (a direction intersecting with the channel width direction) of the basic cells (9).

Abstract: An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).

Abstract: A first baffle plate is approximately annular and disc-like, and one side of the plate is close to and faces on an engine block side face of a flywheel and an outer periphery of the plate is close to and faces on an inner peripheral surface of a clutch housing. A second baffle plate is approximately annular and disc-like, and one side of the plate is close to and faces on an opposite-to-pressure-plate side face of a clutch cover and an outer periphery of the plate is close to and faces on the inner peripheral surface of the clutch housing. A through hole penetrating the flywheel in its axial direction is formed on the flywheel at a position around an inner periphery of the first baffle plate.

Abstract: An inverter circuit (I.sub.3) is disclosed which includes a P-channel MOSFET (3) and a N-channel MOSFET (4) connected in series between a power supply (V.sub.DD) and a ground (GND). The inverter circuit further includes a P-channel MOSFET (5) and a N-channel MOSFET (6) connected in parallel between the gates of the FETs (3) and (4). The FETs (3) and (4) have their gates connected to receive testing mode signals (T.sub.E). In a testing mode operation, the FET (6) is rendered conductive to allow an input signal to be applied to the gate of the FET (4) through the FET (6). The FET (4), having an on-resistance lower than the FET (3), is driven into conduction in response to the output signal applied through the FET (6), thereby providing a slowly rising output signal. The slow rising output signal is free from undershoot or ringing.

Abstract: An outer wall structure of a torque converter or the like including an input housing (1) having an end portion (2), and a pump impeller shell 4 having an end portion (5) fixed to the end portion of the input housing (1). one (5) of the end portions (2, 5) is provided at the outer peripheral surface with a surface portion (15) of a relatively small diameter and a surface portion (16) of a relatively large diameter. A space (27) for accumulating spatter therein is formed between an inner peripheral surface (20) of the other end portion (2) and the surface portion (15) of the relative small diameter.

Abstract: An apparatus for measuring shapes, comprises a scanner, having a plurality of arms for holding an object the shape of which is to be measured, and a turntable to which one end of each of the arms is fixed; and a device for forming a silhouette image of the object including a first optical system which has an optical axis parallel to a rotating axis of the turntable and which has a light source and a light receiving unit confronting each other to allow the object to be in between the light source and the light receiving unit of the first optical system, and a second optical system which has another optical axis substantially at a right angle to the rotating axis of the turntable and which has another light source and another light receiving unit confronting each other to allow the object to be in between the light source and the light receiving unit of the second optical system.

Abstract: In systems which process frequency modulated carrier waves, such as video disc systems, video tape recorder/playback systems and radio systems, there are occasions where the FM signal suddenly drops to a low level. In the case of FM audio signals, these sudden drops result in objectionable tics and pops in the demodulated audio output. The apparatus described herein reduces these objectionable noises by utilizing a variable impedance in connection with a deemphasis circuit in the main signal path. Upon the occurrence of a signal dropout, a defect indication signal is provided to the variable impedance device. The deemphasis circuit has an overall time constant which includes the variable impedance device and which varies in accordance with the detected signal dropouts so as to provide a substantially smooth demodulated output signal whereby tics and pops, in the output audio signal, are substantially removed.