Patents by Inventor Yoshihiro Seguchi

Yoshihiro Seguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11226530
    Abstract: A pixel electrode is formed from a transparent conducting film. A gate insulating layer includes a region including a portion of a thin-film transistor that makes contact with a semiconductor layer and a thinned region. The pixel electrode is disposed over a part of the thinned region. A dielectric layer is in direct contact with another part of the thinned region. An upper surface of the gate insulating layer has a stepped portion. The stepped portion includes a stepped portion that extends flush with a side surface of a lower layer of a drain electrode. The pixel electrode extends over at least a part of the stepped portion and at least a part of the side surface of the lower layer of the drain electrode from above the thinned region and is connected to an upper layer of the drain electrode.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: January 18, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yoshihiro Seguchi
  • Publication number: 20210191207
    Abstract: A pixel electrode is formed from a transparent conducting film. A gate insulating layer includes a region including a portion of a thin-film transistor that makes contact with a semiconductor layer and a thinned region. The pixel electrode is disposed over a part of the thinned region. A dielectric layer is in direct contact with another part of the thinned region. An upper surface of the gate insulating layer has a stepped portion. The stepped portion includes a stepped portion that extends flush with a side surface of a lower layer of a drain electrode. The pixel electrode extends over at least a part of the stepped portion and at least a part of the side surface of the lower layer of the drain electrode from above the thinned region and is connected to an upper layer of the drain electrode.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 24, 2021
    Inventor: Yoshihiro SEGUCHI
  • Patent number: 10175518
    Abstract: There are provided a display device including a highly reliable wiring having excellent adhesion to an insulating film, and a method for manufacturing the same. A molybdenum-niobium layer has good adhesion to an insulating film, and thus, a first wiring having the molybdenum-niobium layer as an upper layer wiring is tightly adhered to a gate insulating film which is formed on the surface of the upper layer wiring. When there is a need to exchange a semiconductor chip mounted on a connection terminal that is provided at an end portion of a wiring such as a gate lead line or a source lead line formed of the first wiring, an ACF which was used for pressure-bonding of the semiconductor chip remains on the connection terminal even if the semiconductor chip is peeled off.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: January 8, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hidenobu Kimoto, Tetsuya Tarui, Yoshihiro Seguchi, Takehisa Sugimoto
  • Patent number: 9869917
    Abstract: An active matrix substrate in a liquid crystal panel of an FFS mode has a data line 24 including an amorphous Si film 122, an n+amorphous Si film 123, a main conductor part 133, and an IZO film 141. The main conductor part 133 and the IZO film 141 are etched at a portion close to the end of a covered region of a photoresist 142, to form the n+amorphous Si film 123 larger than the main conductor part 133 and the IZO film 141. A pattern of a photomask for a source layer is made larger than a pattern of a photomask for a pixel electrode layer, to form the amorphous Si film 122 larger than the n+amorphous Si film 123. The main conductor part 133 is formed of a molybdenum-based material, and in a layer over the data line 24, two-layered protective insulating films are formed such that a compressive stress is generated in one film and a tensile stress is generated in the other film. Accordingly, a high-yield active matrix substrate having a common electrode is provided.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 16, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hidenobu Kimoto, Tetsuya Tarui, Yoshihiro Seguchi, Takehisa Sugimoto
  • Publication number: 20170219899
    Abstract: An active matrix substrate for a liquid crystal panel of an FFS mode includes gate lines, data lines, pixel circuits each including a switching element and a pixel electrode, a protective insulating film formed in a layer over these elements, and a common electrode 30 formed in a layer over the protective insulating film. The common electrode 30 has slits 31 corresponding to the pixel electrode, for generating a lateral electric field to be applied to a liquid crystal layer. In the common electrode 30, a cutout above data line 32 having a portion extending in the same direction as that of the data line is formed in a region including a part of a placement region for the data line. On a counter substrate, a black matrix is formed in a position that faces a region including placement regions for the gate line, the data line, the switching element, and the cutout above data line 32. This reduces display failure caused by a load of the data line.
    Type: Application
    Filed: June 24, 2015
    Publication date: August 3, 2017
    Inventors: Tomoo FURUKAWA, Junichi MORINAGA, Masakatsu TOMINAGA, Hidenobu KIMOTO, Yoshihiro SEGUCHI
  • Publication number: 20170139296
    Abstract: A first wiring of the present invention is a wiring having a two-layer structure including a lower layer wiring and an upper layer wiring which is formed to cover an upper surface and both side surfaces of the lower layer wiring, and thus, even if the lower layer wiring includes a part where the line width is reduced and which is nearly disconnected due to a particle or the like attached at the time of formation of the lower layer wiring, the probability is extremely low that a particle is attached again, to the upper layer wiring at the time of formation of the upper layer wiring, at a position corresponding to the nearly disconnected part of the lower layer wiring. Moreover, the lower layer wiring and the upper layer wiring are electrically connected to each other.
    Type: Application
    Filed: July 23, 2015
    Publication date: May 18, 2017
    Inventors: Hidenobu KIMOTO, Tetsuya TARUI, Yoshihiro SEGUCHI, Takehisa SUGIMOTO
  • Publication number: 20170139298
    Abstract: An active matrix substrate in a liquid crystal panel of an FFS mode has a data line 24 including an amorphous Si film 122, an n+amorphous Si film 123, a main conductor part 133, and an IZO film 141. The main conductor part 133 and the IZO film 141 are etched at a portion close to the end of a covered region of a photoresist 142, to form the n+amorphous Si film 123 larger than the main conductor part 133 and the IZO film 141. A pattern of a photomask for a source layer is made larger than a pattern of a photomask for a pixel electrode layer, to form the amorphous Si film 122 larger than the n+amorphous Si film 123. The main conductor part 133 is formed of a molybdenum-based material, and in a layer over the data line 24, two-layered protective insulating films are formed such that a compressive stress is generated in one film and a tensile stress is generated in the other film. Accordingly, a high-yield active matrix substrate having a common electrode is provided.
    Type: Application
    Filed: June 24, 2015
    Publication date: May 18, 2017
    Inventors: Hidenobu KIMOTO, Tetsuya TARUI, Yoshihiro SEGUCHI, Takehisa SUGIMOTO
  • Publication number: 20170139260
    Abstract: There are provided a display device including a highly reliable wiring having excellent adhesion to an insulating film, and a method for manufacturing the same. A molybdenum-niobium layer has good adhesion to an insulating film, and thus, a first wiring having the molybdenum-niobium layer as an upper layer wiring is tightly adhered to a gate insulating film which is formed on the surface of the upper layer wiring. When there is a need to exchange a semiconductor chip mounted on a connection terminal that is provided at an end portion of a wiring such as a gate lead line or a source lead line formed of the first wiring, an ACF which was used for pressure-bonding of the semiconductor chip remains on the connection terminal even if the semiconductor chip is peeled off.
    Type: Application
    Filed: July 23, 2015
    Publication date: May 18, 2017
    Inventors: Hidenobu KIMOTO, Tetsuya TARUI, Yoshihiro SEGUCHI, Takehisa SUGIMOTO
  • Publication number: 20150301935
    Abstract: A program counter (12) updates an address by adding a first value or a second value. A code select circuit (14) selects, in accordance with the address of the program counter (12), one of an insert code retained in an insert code register set block (17) and corresponding to the address specified by the program counter (12), and an original code stored in a flash control code ROM (13) and having the address specified by the program counter (12). An instruction execution unit (15) executes the selected code. At least one of a plurality of original codes and the insert code is a multicycle instruction. The program counter (14) stops update of the address when the multicycle instruction is executed.
    Type: Application
    Filed: March 2, 2012
    Publication date: October 22, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Tamiyu KATO, Yukiko MARUYAMA, Shinya IZUMI, Kiyoshi NAKAKIMURA, Yoshihiro SEGUCHI
  • Patent number: 6128245
    Abstract: A memory capacity switching method for switching capacities of an accessible memory in a semiconductor device 1 which comprises on a single chip the memory 2, a capacity switching signal generating circuit 4 for generating a capacity switching signal, and a control circuit 5 for switching capacities of the memory on the basis of the capacity switching signal. The method comprises the step of setting the capacity switching signal from the capacity switching signal generating circuit 4 either to 0 or to 1 causing the control circuit to switch the memory capacities as needed. The method and the semiconductor device for use therewith combine to shorten the time required for semiconductor device development and to reduce costs in fabricating the device.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: October 3, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshihiro Seguchi
  • Patent number: 5280597
    Abstract: An improved self-timed pipeline processor is provided with self-timed data transfer, thereby making it possible to control exclusively the memory reading and memory writing accesses of individual pipeline stages. The self-timed pipeline processor prohibits memory reading during memory writing and vice versa. In addition, the pipeline processor temporarily prevents the transfer of data to a next-accessing pipeline stage when the memory address presently being accessed is the same as the address to be accessed next, thereby preventing malfunction of the processor.
    Type: Grant
    Filed: March 28, 1991
    Date of Patent: January 18, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hidehiro Takata, Yoshihiro Seguchi, Hisakazu Sato, Shinji Komori
  • Patent number: 4924421
    Abstract: Where the first bit position having a predetermined value; e.g., 1, as viewed from the most significant bit (MSB) or least significant bit (LSB) of the input data, 1 is subtracted from the input data to provide a subtraction result. This subtraction result and the input data are provided to the inputs of an exclusive OR gate is applied to a priority encoder capable of encoding the first bit position having a 1 as viewed from the MSB. The output represents the first bit position having a 1 as viewed from the LSB, thus requiring only a single priority encoder capable of detecting the first bit position having a 1 as viewed from the MSB.
    Type: Grant
    Filed: May 17, 1988
    Date of Patent: May 8, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshihiro Seguchi
  • Patent number: 4755968
    Abstract: A buffer memory device is formed of: a plurality of memory blocks each comprising a register and a comparator for comparing the content of said register and the input data. A control circuit controls the shift of the data of said registers in such a manner that only the contents of said registers from the first memory block to a desired memory block are shifted.
    Type: Grant
    Filed: June 17, 1986
    Date of Patent: July 5, 1988
    Assignee: Mitsubishi Denki Kabushiki
    Inventors: Toyohiko Yoshida, Yoshihiro Seguchi