Abstract: A display driver drives a display in which each pixel includes a light-emitting element, a transistor that supplies current to the light-emitting element, and a capacitor that controls the transistor. To determine the threshold voltage of the transistor, the display driver charges the capacitor to an initial voltage, then allows the capacitor to discharge through the transistor, measures the time that elapses until the capacitor reaches a reference voltage intermediate between the initial voltage and the threshold voltage, and calculates the threshold voltage from the elapsed time. This measurement method is quick and does not require an analog-to-digital converter. The measured values are used to generate correction data to compensate for threshold voltage shifts.

Abstract: A data storage apparatus includes a flash memory and a control unit that controls the rewriting of data in the flash memory. The flash memory is divided into sectors, each of which is completely erasable in a time T. During a rewriting operation, multiple sectors are erased simultaneously for a time U less than T, and new data are written in a sector that has undergone multiple erasures and is now fully erased. The new data typically replace data stored in a sector that proceeds to be erased during multiple rewriting operations. The duration of each rewriting operation is reduced because the erasing process lasts for time U instead of time T.

Abstract: A data storage apparatus includes a flash memory and a control unit that controls the rewriting of data in the flash memory. The flash memory is divided into sectors, each of which is completely erasable in a time T. During a rewriting operation, multiple sectors are erased simultaneously for a time U less than T, and new data are written in a sector that has undergone multiple erasures and is now fully erased. The new data typically replace data stored in a sector that proceeds to be erased during multiple rewriting operations. The duration of each rewriting operation is reduced because the erasing process lasts for time U instead of time T.

Abstract: A data storage apparatus includes a flash memory and a control unit that controls the rewriting of data in the flash memory. The flash memory is divided into sectors, each of which is completely erasable in a time T. During a rewriting operation, multiple sectors are erased simultaneously for a time U less than T, and new data are written in a sector that has undergone multiple erasures and is now fully erased. The new data typically replace data stored in a sector that proceeds to be erased during multiple rewriting operations. The duration of each rewriting operation is reduced because the erasing process lasts for time U instead of time T.

Abstract: A serial data communication machine includes a counter for counting a reference clock and a shift register for receiving incoming and outgoing data. Every time the counter counts the reference clock certain times, which is equal to a first integer determined in accordance with a ratio of a reference clock frequency to a transfer rate, the data stored in the shift register are shifted such that the data are transmitted and received at a rate substantially equal to the transfer rate. The communication machine also includes a clock correction unit. Every time the reference clock is generated certain times, which is equal to a second integer determined in accordance with a difference between the above mentioned ratio and the first integer, the clock correction unit temporarily hinders passage of the reference clock to the counter. Even if one bit time is not a multiple of the reference clock, the communication machine can transfer the data at high speed without increasing the reference clock frequency.

Abstract: An improved method of rewriting data in a memory is provided. A flash memory has a sector partitioned into a plurality of areas. In the flash memory, data are written to a same position in the respective areas. When writing rewrite data, an exclusive-OR of the rewrite data and data at a target position in a first area is taken, and an exclusive-OR of the exclusive-OR data and data at the same position in a second area is taken. Similar steps are repeated in sequence for the rest of the areas. In the course of repeating these steps, when data at the target position of the area concerned are an initial value, then the most recent exclusive-OR data are written to the position in that area.

Abstract: A data storage apparatus includes a flash memory and a control unit that controls the rewriting of data in the flash memory. The flash memory is divided into sectors, each of which is completely erasable in a time T. During a rewriting operation, multiple sectors are erased simultaneously for a time U less than T, and new data are written in a sector that has undergone multiple erasures and is now fully erased. The new data typically replace data stored in a sector that proceeds to be erased during multiple rewriting operations. The duration of each rewriting operation is reduced because the erasing process lasts for time U instead of time T.

Abstract: A serial data communication machine includes a counter for counting a reference clock and a shift register for receiving incoming and outgoing data. Every time the counter counts the reference clock certain times, which is equal to a first integer determined in accordance with a ratio of a reference clock frequency to a transfer rate, the data stored in the shift register are shifted such that the data are transmitted and received at a rate substantially equal to the transfer rate. The communication machine also includes a clock correction unit. Every time the reference clock is generated certain times, which is equal to a second integer determined in accordance with a difference between the above mentioned ratio and the first integer, the clock correction unit temporarily hinders passage of the reference clock to the counter. Even if one bit time is not a multiple of the reference clock, the communication machine can transfer the data at high speed without increasing the reference clock frequency.

Abstract: A rectifier circuit 30 of a voltage genetator 100 rectifys a alternating current signals through the use of the electromagnetic induction of a coil 11, the rectified signals are boosied by rectifying the voltage of nodes of the coil 11 by capacitors 21 and 22, and the voltage genetrator 100 generates a predetermined voltage by smoothing the boosted signals by a capacitor 17.

Abstract: A random number generating system and its method for generating very irregular random numbers without an increase of a consumed current and an expansion of a chip in size, comprising a random number generator 202 for generating random numbers and a signal line 201 for transmitting data to functional blocks arranged outside the random number generator 202, wherein the random number generator 202 has a first shift register 203, a second shift register 204, and a logic device 205 for executing a logical operation between an output from the first shift register 203 and data transmitted through the signal line 201 and then inputting a result of the operation to the second shift register 204 and generates random numbers by using a data value transmitted to the functional block arranged outside the random number generator 202.

Abstract: A rectifier circuit 30 of a voltage genetator 100 rectifys a alternating current signals through the use of the electromagnetic induction of a coil 11, the rectified signals are boosied by rectifying the voltage of nodes of the coil 11 by capacitors 21 and 22, and the voltage genetrator 100 generates a predetermined voltage by smoothing the boosted signals by a capacitor 17.

Abstract: A frequency counter 1 includes a binary counter section 11 having a binary counter 20 for counting up frequency data, and a EEPROM counter section 12 having an EEPROM 40 containing frequency data. In a frequency count processing, frequency data of the EEPROM 40 are loaded into the binary counter 20. The binary counter 20 executes count up by a specified frequency on the loaded frequency data. The counted up frequency data are written into the EEPROM 40 to update the frequency data of the EEPROM 40. In one frequency count process, rewriting of the EEPROM 40 is completed once, which means that the number of time the EEPROM 40 is rewritten is reduced.

Abstract: An integrated circuit embedded in a smart card has a rewritable non-volatile memory in which an instruction file is stored. A control logic circuit in the integrated circuit converts random data into authentication data by executing instructions read from the instruction file, preferably by controlling a simplified data processing circuit having a shift register, an exclusive-OR logic circuit, and specialized bit operation circuits. A card issuer issuing smart cards including this integrated circuit writes different instruction files in different smart cards, thereby enhancing the security of the smart cards.

Abstract: A rectifier circuit of a voltage genetator rectifies alternating current signals provided through electromagnetic induction of a coil. The rectified signals are boosted by rectifying the voltage of nodes of the coil by capacitors, and the voltage genetrator generates a predetermined voltage by smoothing the boosted signals using a capacitor.

Abstract: A rectifier circuit 30 of a voltage genetator rectifies alternating current signals provided through electromagnetic induction of a coil. The rectified signals are boosted by rectifying the voltage of nodes of the coil by capacitors, and the voltage genetator generates a predetermined voltage by smoothing the boosted signals using a capacitor.

Abstract: A communication system can maintain high security in communication between a communication apparatus and a terminal. The communication system includes the communication apparatus and the terminal provided with a memory unit for storing data for specifying function of the communication apparatus. The communication apparatus and the terminal include random number generators for generating random numbers, encryption/decryption key preparing units for preparing encryption/decryption keys on the basis of both random numbers and generated by the respective random number generators of the communication apparatus and the terminal and a secret key held in common by the communication apparatus and the terminal, and encryption/decryption processing units for encrypting or decrypting communication data between the communication apparatus and the terminal containing the data by means of the encryption/description key, respectively.

Abstract: A call-unit count device according to the present invention comprises a memory circuit having a high-order level and a low-order level composed of n (n: integer greater than or equal to 2) bits and wherein all the bits each indicative of the initial value and placed in the low-order level are changed to reversed values bit by bit each time a one call-unit add command is given, all the bits in the low-order level, which have been brought to the reversed values, are returned to the initial value bit by bit each time the one call-unit add command is given, and values stored in the high-order level are changed upon a carry from the low-order level to the high-order level.

Abstract: A random number generated from a host device upon a first mutual authentication or a random number obtained by processing the generated random number is stored in a random number storage area of an IC apparatus and used for a subsequent mutual authentication.

Abstract: The present invention provides a method of controlling an IC card reader/writer which is low in cost and simple in structure using a UART which is a universal transmission circuit. A transmission line and a receive line of the UART are directly connected to each other for use as an SIO line of said IC card. In a command transmission/receive control, at the time of transmission processing the same character as a preceding one is transmitted when a framing error is detected and a next character is transmitted when an echo back is normally received upon reception of an echo back character after transmission of one character. At the time of a succeeding receive processing, the same command processing is executed again upon termination of the transmission/receive processing when a parity error is generated in a received character.

Abstract: An IC card device includes a card base, at least one integrated circuit disposed on the card base, and communication circuitry disposed on the card base and coupled to the at least one integrated circuit, for transferring signals between the at least one integrated circuit and an external device. The at least one integrated circuit includes a first reloadable memory having a command table area for storing command tables, a second read-only memory for storing a non-reloadable command table, and selecting circuitry, operatively coupled to the first memory and the second memory, for selecting either the non-reloadable command table stored in the second memory or a command table stored in the command table area of the first memory. The command table of the first memory and the command table of the second memory store command class designations which designate the class of each of the commands, and store command code designations which designate the operation corresponding to each of the commands.