Abstract: To form a recess defining a channel region in a SOI layer, a LOCOS oxide film is formed on a surface of the SO layer and then removed. Then, side walls of CVD oxide is formed on side surfaces defining an opening of a LOCOS oxide restraining film. Then, a gate oxide film is formed on an exposed surface of the SOI layer inside the opening. Then, CVD polycrystalline silicon is formed on the whole wafer surface, and then etched back to form a gate electrode of polycrystalline silicon inside the opening. At this time, a top surface of the gate electrode is at a level lower than a top surface of the restraining film. Next, the restraining film and the side walls are removed and ion implantation into the SOI layer is performed using the gate electrode as a mask to thereby form a source and a drain region. Then, side walls are formed on side surfaces of the gate electrode, and a silicide film is formed on the gate electrode and the source and drain regions.

Abstract: A ferroelectric thin film is produced on a substrate placed in an oxygen gas atmosphere within a reaction chamber. Evaporated source materials (organic metal compounds) are separately introduced in a predetermined sequence into the reaction chamber to produce a PZT or PLZT layer structure having an estimated stoichiometric composition. This cycle of introduction of the source materials is repeated continuously to produce a PZT or PLZT ferroelectric thin film having a predetermined number of PZT or PLZT layer structures piled on the substrate.