Abstract: There is provided an information processing device for measuring a dimension of an object to be measured in a low-load calculation processing. A handy terminal includes a depth map sensor block for generating a depth map of an object to be measured by use of a depth map sensor, and a coordinate transformation/side length calculation unit that measures a dimension of the object to be measured based on the depth map. The handy terminal may further includes a delivery fee calculation unit that calculates a delivery fee of the object to be measured based on the dimension.

Abstract: In a semiconductor integrated circuit, a detection confirmation circuit sets the logical level of a second signal according to the logical level of a first signal observed after a lapse of a predetermined time since detection of insertion/removal of a cable for peripheral equipment. The semiconductor integrated circuit operates in a standby mode in which only the insertion/removal detection circuit operates if no cable for peripheral equipment is connected, in a repeater mode in which only PHY operates if a cable for peripheral equipment is connected and CPU is in the suspended state, and in a normal mode in which both PHY and LINK operate if a cable for peripheral equipment is connected and a CPU is in the operating state.

Abstract: The present invention provides a transmitter capable of reducing the occurrence of noise when switching from the SD signal to the HD signal, for example. A microcomputer (151) controls a 10-times multiplication PLL (13) to increase the amount of jitter of a multiplied clock (CLK1×10) upon signal switching, i.e., when switching the frequency of an input clock (CLK1) from one to another. Alternatively, it controls a phase adjustment section (31) to increase the amount of jitter of a transmit clock (CLK2). Alternatively, it controls a fixed data producing section (61) to set transmit data (DATA2) to predetermined fixed data stored in a fixed data storing section (62).

Abstract: A clock control circuit 22 in a control circuit 21 provided in a transmitter 25 controls a gate circuit 12 based on an instruction from a microcomputer 32 to stop the output of the clock to a cable 115 for a first predetermined period of time. Then, a read-out circuit in the microcomputer 32 accesses an EDID 31 stored in an information storing circuit of a receiver 43 via the cable 115, and specifies the first predetermined period of time based on the EDID 31. A reconfiguration circuit 42 provided in the receiver 43 counts the clock-holding state, and resets at least one of the receiver 43 and a TV 114 if the clock has been stopped for a second predetermined period of time. This reset operation suppresses the display of noise on the TV 114. Therefore, the occurrence of noise due to mis-latching between the clock and the data can be reduced even after a signal switching that entails a change in the clock frequency.

Abstract: A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus.

Abstract: The multi-initiator control unit for performing packet-unit communication with each of a plurality of devices connected via a transmission line includes: a packet filter for analyzing a received packet and outputting the results; a plurality of command control circuits each for controlling a command processing sequence performed with the corresponding device; a multi-control circuit for giving sequence execution permission to one of the plurality of command control circuits; and a packet processing circuit for generating a packet containing information output by the permission-given command control circuit and outputting the packet for transmission, and also outputting a received packet according to the analysis results output by the packet filter.

Abstract: The multi-initiator control unit for performing packet-unit communication with each of a plurality of devices connected via a transmission line includes: a packet filter for analyzing a received packet and outputting the results; a plurality of command control circuits each for controlling a command processing sequence performed with the corresponding device; a multi-control circuit for giving sequence execution permission to one of the plurality of command control circuits; and a packet processing circuit for generating a packet containing information output by the permission-given command control circuit and outputting the packet for transmission, and also outputting a received packet according to the analysis results output by the packet filter.

Abstract: In a semiconductor integrated circuit, a detection confirmation circuit sets the logical level of a second signal according to the logical level of a first signal observed after a lapse of a predetermined time since detection of insertion/removal of a cable for peripheral equipment. The semiconductor integrated circuit operates in a standby mode in which only the insertion/removal detection circuit operates if no cable for peripheral equipment is connected, in a repeater mode in which only PHY operates if a cable for peripheral equipment is connected and CPU is in the suspended state, and in a normal mode in which both PHY and LINK operate if a cable for peripheral equipment is connected and a CPU is in the operating state.

Abstract: In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for controlling a command issue sequence, a packet processing circuit for assembling operation request blocks (ORB) into a transmission packet and extracting a status from a received packet; buffer for storing a command ORB provided by the CPU; a buffer for storing a management ORB provided by the CPU; a buffer for storing a status received for an issued management ORB and providing the status to the CPU; and a buffer for command for storing a status received for an issued command ORB and providing the status to the CPU.

Abstract: A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus.

Abstract: If a packet processing controller at a consumer node has failed to process a received packet within a predetermined amount of time, a packet processing control timer detects a time-out and informs a CPU of that. In response, the CPU issues packet processing suspend instruction and packet transmit instruction for the controller by way of a register. In accordance with these instructions, the controller suspends the current packet processing and produces header and data for a WRS packet, which is transmitted to a producer node through a bus. In this manner, a packet can be processed without causing a time-out at the producer node.

Abstract: A data transfer device which set an address of page as transfer destination and transfer data to the page. In the data transfer device to which the present invention is applied, an address and page length of a page are acquired on the basis of an address of a page table specified by a read command. Then, transfer information including the address of transfer source, transfer data length and address of transfer destination of data is set according to page element of page as transfer destination page. Then, it is judged whether the transfer destination page and other page form a continuous area. And if it is judged that the continuous area is formed, transfer information will be changed. Data transfer is effected on the basis of changed transfer information. That reduces the need to set the other area at the transfer destination and thus the transfer efficiency improves.

Abstract: A reception buffer, a transmission buffer, a transmission-reception buffer, a reception filter, a transmission filter and a packet processor are provided. If a response packet paired with a request packet has been received during a data exchange operation, then the reception filter stores the response packet received on the transmission-reception buffer and informs the packet processor of response detected. Alternatively, if a packet that has nothing to do with the current data exchange operation has been received, then the reception filter stores the received packet on the reception buffer and issues a suspension instruction to the packet processor. And when a transaction being carried out at the time of reception is completed, the packet processor suspends the data exchange. In this manner, the overheads involved with firmware processing by a central processing unit can be reduced and data can be exchanged at higher speeds.

Abstract: A reception buffer, a transmission buffer, a transmission-reception buffer, a reception filter, a transmission filter and a packet processor are provided. If a response packet paired with a request packet has been received during a data exchange operation, then the reception filter stores the response packet received on the transmission-reception buffer and informs the packet processor of response detected. Alternatively, if a packet that has nothing to do with the current data exchange operation has been received, then the reception filter stores the received packet on the reception buffer and issues a suspension instruction to the packet processor. And when a transaction being carried out at the time of reception is completed, the packet processor suspends the data exchange. In this manner, the overheads involved with firmware processing by a central processing unit can be reduced and data can be exchanged at higher speeds.

Abstract: Reception buffer, transmission buffer, transmission-reception buffer, reception filter and transmission filter are provided. The reception filter determines where a received packet should be stored based on the contents of the received packet. Specifically, in executing a READ command, a response packet, which is returned in response to a data transmission packet, is detected by the reception filter. Received packets of the other types are stored on the reception buffer. In executing a WRITE command, a data request packet is transmitted from the transmission buffer. A data reception packet responding to the data request packet is stored by the reception filter on the transmission-reception buffer. Received packets of the other types are stored on the reception buffer. The capacity of the transmission-reception buffer is twice as large as the size of a maximum transferable packet. Thus, overhead can be reduced and yet data can be transferred at higher speeds.

Abstract: In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for controlling a command issue sequence, a packet processing circuit for assembling operation request blocks (ORB) into a transmission packet and extracting a status from a received packet; buffer for storing a command ORB provided by the CPU; a buffer for storing a management ORB provided by the CPU; a buffer for storing a status received for an issued management ORB and providing the status to the CPU; and a buffer for command for storing a status received for an issued command ORB and providing the status to the CPU.

Abstract: A data transfer device which set an address of page as transfer destination and transfer data to the page. In the data transfer device to which the present invention is applied, an address and page length of a page are acquired on the basis of an address of a page table specified by a read command. Then, transfer information including the address of transfer source, transfer data length and address of transfer destination of data is set according to page element of page as transfer destination page. Then, it is judged whether the transfer destination page and other page form a continuous area. And if it is judged that the continuous area is formed, transfer information will be changed. Data transfer is effected on the basis of changed transfer information. That reduces the need to set the other area at the transfer destination and thus the transfer efficiency improves.

Abstract: The multi-initiator control unit for performing packet-unit communication with each of a plurality of devices connected via a transmission line includes: a packet filter for analyzing a received packet and outputting the results; a plurality of command control circuits each for controlling a command processing sequence performed with the corresponding device; a multi-control circuit for giving sequence execution permission to one of the plurality of command control circuits; and a packet processing circuit for generating a packet containing information output by the permission-given command control circuit and outputting the packet for transmission, and also outputting a received packet according to the analysis results output by the packet filter.

Abstract: If a packet processing controller at a consumer node has failed to process a received packet within a predetermined amount of time, a packet processing control timer detects a time-out and informs a CPU of that. In response, the CPU issues packet processing suspend instruction and packet transmit instruction for the controller by way of a register. In accordance with these instructions, the controller suspends the current packet processing and produces header and data for a WRS packet, which is transmitted to a producer node through a bus. In this manner, a packet can be processed without causing a time-out at the producer node.

Abstract: A plurality of cells which have input terminals and output terminals on four sides are divided into a plurality of groups of cells. The plurality of cells are placed in an array form at positions which are either adjacent or nonadjacent. A plurality of groups of cells are placed one after another such that the resulting layout becomes substantially rectangular or square. Power buses are routed parallel to each other, and power supply lines are routed from the power buses to cells. Data lines are routed between the terminals of the cells.