Patents by Inventor Yoshihiro TENO

Yoshihiro TENO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9768685
    Abstract: Bootstrap circuit includes: a first transistor of first conductivity type having a first main electrode, a second main electrode and a control electrode connected to a first power supply terminal, a first node, and a second node, respectively; a second transistor of the first conductivity type having a first main electrode, a second main electrode, and a control electrode connected to the first power supply terminal, the second node and the first node, respectively; a first capacitor having a first end connected to the first node and a second end where a first boost pulse is applied; a second capacitor having a first end connected to the second node and a second end where a second boost pulse having opposite polarity to the first boost pulse is applied; and a boost output terminal which outputs boost voltage higher than first power supply voltage supplied to the first power supply terminal.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: September 19, 2017
    Assignee: Rohm Co., Ltd.
    Inventor: Yoshihiro Teno
  • Patent number: 9595348
    Abstract: A memory circuit includes: a control part configured to output a control signal; a fuse circuit which is driven by the control signal and is configured to output a fuse signal whose signal level is determined based on a state of a first fuse element; and a holding circuit configured to update and hold a signal based on the fuse signal in response to the control signal output from the control part and output the held signal as an output signal.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: March 14, 2017
    Assignee: Rohm Co., Ltd.
    Inventor: Yoshihiro Teno
  • Publication number: 20160079848
    Abstract: Bootstrap circuit includes: a first transistor of first conductivity type having a first main electrode, a second main electrode and a control electrode connected to a first power supply terminal, a first node, and a second node, respectively; a second transistor of the first conductivity type having a first main electrode, a second main electrode, and a control electrode connected to the first power supply terminal, the second node and the first node, respectively; a first capacitor having a first end connected to the first node and a second end where a first boost pulse is applied; a second capacitor having a first end connected to the second node and a second end where a second boost pulse having opposite polarity to the first boost pulse is applied; and a boost output terminal which outputs boost voltage higher than first power supply voltage supplied to the first power supply terminal
    Type: Application
    Filed: September 10, 2015
    Publication date: March 17, 2016
    Inventor: Yoshihiro Teno
  • Publication number: 20160035435
    Abstract: A memory circuit includes: a control part configured to output a control signal; a fuse circuit which is driven by the control signal and is configured to output a fuse signal whose signal level is determined based on a state of a first fuse element; and a holding circuit configured to update and hold a signal based on the fuse signal in response to the control signal output from the control part and output the held signal as an output signal.
    Type: Application
    Filed: July 27, 2015
    Publication date: February 4, 2016
    Inventor: Yoshihiro TENO