Patents by Inventor Yoshihiro Tsukidate
Yoshihiro Tsukidate has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7593266Abstract: Example embodiments provide a semiconductor memory device and a method of verifying the same. The semiconductor memory device may include: a memory including a plurality of memory cells; a verifier determining a program state of the memory cell in the memory; and/or an address/program controller controlling the memory and the verifier. Example embodiments include making the memory start a suspend operation during an operation of the memory cell, and/or starting a verify operation when the suspend operation terminates. The address/program controller may start the operation on the memory cell if it is determined that a repeat operation is necessary, and may start the program operation on the next memory cell if it is determined that a repeat operation is unnecessary. The memory operation mode may be one in which a verify operation is not performed before programming.Type: GrantFiled: June 26, 2007Date of Patent: September 22, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Makoto Senoo, Kazunari Kido, Shunichi Toyama, Yoshihiro Tsukidate
-
Publication number: 20080123428Abstract: Example embodiments provide a semiconductor memory device and a method of verifying the same. The semiconductor memory device may include: a memory including a plurality of memory cells; a verifier determining a program state of the memory cell in the memory; and/or an address/program controller controlling the memory and the verifier. Example embodiments include making the memory start a suspend operation during an operation of the memory cell, and/or starting a verify operation when the suspend operation terminates. The address/program controller may start the operation on the memory cell if it is determined that a repeat operation is necessary, and may start the program operation on the next memory cell if it is determined that a repeat operation is unnecessary. The memory operation mode may be one in which a verify operation is not performed before programming.Type: ApplicationFiled: June 26, 2007Publication date: May 29, 2008Inventors: Makoto Senoo, Kazunari Kido, Shunichi Toyama, Yoshihiro Tsukidate
-
Patent number: 7321513Abstract: A semiconductor device includes at least one reference cell (6), a cascode circuit (8) that has at least two current mirror circuits (30, 33 and 30, 34) and outputs voltages dependent on a current flowing through the at least one reference cell (6) to at least two output paths (55, 56), and a switch (20) that selectively connects the at least two output paths (55, 56) to a given output terminal (27).Type: GrantFiled: March 28, 2006Date of Patent: January 22, 2008Assignee: Spansion LLCInventor: Yoshihiro Tsukidate
-
Publication number: 20070035993Abstract: A semiconductor device includes at least one reference cell (6), a cascode circuit (8) that has at least two current mirror circuits (30, 33 and 30, 34) and outputs voltages dependent on a current flowing through the at least one reference cell (6) to at least two output paths (55, 56), and a switch (20) that selectively connects the at least two output paths (55, 56) to a given output terminal (27).Type: ApplicationFiled: March 28, 2006Publication date: February 15, 2007Inventor: Yoshihiro Tsukidate
-
Patent number: 7061809Abstract: A nonvolatile semiconductor memory device includes a plurality of blocks each having a memory cell array, a reference cell, a signal line that supplies a reference signal read from the reference cell to each of the plurality of blocks, a reference load circuit which is provided in each of the plurality of blocks, and exerts a load on the reference signal that is identical to a load imposed on data that is read from the memory cell array, and a sensing circuit which is provided in each of the plurality of blocks, and compares the data with the reference signal having the load imposed thereon by the reference load circuit so as to sense the data.Type: GrantFiled: August 5, 2003Date of Patent: June 13, 2006Inventor: Yoshihiro Tsukidate
-
Patent number: 6865133Abstract: A memory circuit has a plurality of blocks which further comprises a plurality of regular sectors and a spare sector, wherein each sector further comprises a plurality of memory cells, and when a regular sector in a first block is defective, this defective regular sector is replaced with a spare sector in a second block. And responding to an address to be supplied, the regular sector corresponding to the supplied address in the first block and the spare selector in the second block are selected simultaneously during a first period, and after the first period, selection of one of the regular sector and the spare sector is maintained according to the result of redundancy judgment on whether the supply address matches with the redundant address.Type: GrantFiled: September 2, 2003Date of Patent: March 8, 2005Assignee: Fujitsu LimitedInventors: Yoshihiro Tsukidate, Kazuhiro Kurihara, Yasushi Kasa, Tsutomu Nakai, Andy Cheung
-
Patent number: 6777799Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: GrantFiled: July 22, 2003Date of Patent: August 17, 2004Assignee: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Takao Nishimura
-
Publication number: 20040109371Abstract: A memory circuit has a plurality of blocks which further comprises a plurality of regular sectors and a spare sector, wherein each sector further comprises a plurality of memory cells, and when a regular sector in a first block is defective, this defective regular sector is replaced with a spare sector in a second block. And responding to an address to be supplied, the regular sector corresponding to the supplied address in the first block and the spare selector in the second block are selected simultaneously during a first period, and after the first period, selection of one of the regular sector and the spare sector is maintained according to the result of redundancy judgment on whether the supply address matches with the redundant address.Type: ApplicationFiled: September 2, 2003Publication date: June 10, 2004Inventors: Yoshihiro Tsukidate, Kazuhiro Kurihara, Yasushi Kasa, Tsutomu Nakai, Andy Cheung
-
Publication number: 20040051119Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: ApplicationFiled: July 22, 2003Publication date: March 18, 2004Applicant: FUJITSU LIMITEDInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Takao Nishimura
-
Publication number: 20040052119Abstract: A nonvolatile semiconductor memory device includes a plurality of blocks each having a memory cell array, a reference cell, a signal line that supplies a reference signal read from the reference cell to each of the plurality of blocks, a reference load circuit which is provided in each of the plurality of blocks, and exerts a load on the reference signal that is identical to a load imposed on data that is read from the memory cell array, and a sensing circuit which is provided in each of the plurality of blocks, and compares the data with the reference signal having the load imposed thereon by the reference load circuit so as to sense the data.Type: ApplicationFiled: August 5, 2003Publication date: March 18, 2004Applicant: FUJITSU LIMITEDInventor: Yoshihiro Tsukidate
-
Patent number: 6621169Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: GrantFiled: August 29, 2001Date of Patent: September 16, 2003Assignee: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
-
Patent number: 6377491Abstract: This invention is nonvolatile memory that has an ordinary memory cell region wherein ordinary data is stored and an erase information storage memory region wherein the information that shows the status of the erase operation is stored. The erase information storage memory region comprises nonvolatile memory that can store the information even when the power is cut. Preferably, the erase information storage memory region can store erase information in the memory block units in which the erase operation is executed. Further preferably, the erase information storage memory region is able to store erase information for at least the three statuses that are involved in erase operations: erase operation start status, preprogramming end status, and erase operation complete status.Type: GrantFiled: February 1, 2001Date of Patent: April 23, 2002Assignee: Fujitsu LimitedInventors: Hiroshi Otani, Makoto Igarashi, Yoshihiro Tsukidate
-
Publication number: 20020027295Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: ApplicationFiled: August 29, 2001Publication date: March 7, 2002Applicant: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
-
Publication number: 20010019501Abstract: This invention is nonvolatile memory that has an ordinary memory cell region wherein ordinary data is stored and an erase information storage memory region wherein the information that shows the status of the erase operation is stored. The erase information storage memory region comprises nonvolatile memory that can store the information even when the power is cut. Preferably, the erase information storage memory region can store erase information in the memory block units in which the erase operation is executed. Further preferably, the erase information storage memory region is able to store erase information for at least the three statuses that are involved in erase operations: erase operation start status, preprogramming end status, and erase operation complete status.Type: ApplicationFiled: February 1, 2001Publication date: September 6, 2001Applicant: FUJITSU LIMITEDInventors: Hiroshi Otani, Makoto Igarashi, Yoshihiro Tsukidate