Abstract: It is intended to provide a substrate structure ensuring a shielding property and a heat discharge property of a resin part that collectively covers a plurality of electronic components and capable of downsizing, thinning, and a reduction in number of components. The substrate structure 20 of the first embodiment is provided with a substrate 21, a plurality of electronic components 22 mounted along the substrate 21, and a resin part 25 that covers the electronic components 22 and is in close contact with the substrate 21. In the substrate structure 20, the resin part 25 is provided with a reinforcing heat discharge layer 26 covering the electronic components 22 and having a heat conductivity and a reinforcing property and a shield layer 27 covering the reinforcing heat discharge layer 26, and a surface o28 of the shield layer 27 is formed into a predetermined shape corresponding to a surface structure of the display device 30 adjacent to the resin part 25.

Abstract: It is intended to provide a substrate structure ensuring a shielding property and a heat discharge property of a resin part that collectively covers a plurality of electronic components and capable of downsizing, thinning, and a reduction in number of components. The substrate structure 20 of the first embodiment is provided with a substrate 21, a plurality of electronic components 22 mounted along the substrate 21, and a resin part 25 that covers the electronic components 22 and is in close contact with the substrate 21. In the substrate structure 20, the resin part 25 is provided with a reinforcing heat discharge layer 26 covering the electronic components 22 and having a heat conductivity and a reinforcing property and a shield layer 27 covering the reinforcing heat discharge layer 26, and a surface o28 of the shield layer 27 is formed into a predetermined shape corresponding to a surface structure of the display device 30 adjacent to the resin part 25.

Abstract: A parallel to serial converter for convering incoming parallel, byte sized, data supplied at a first data rate to single bit serial data includes a shift register in which several bytes of the incoming data are stored simultaneously and thereafter serially transmitted therefrom. The parallel to serial converter includes latching devices in which the incoming data bytes are stored prior to being transferred to the shift register. Since successively arriving bytes of data are stored in successively selected ones of the latching devices, the data rate (device speed) of the latches is permitted to be only a fraction of the first data rate associated with the incoming bytes of data resulting in a fast, yet inexpensive, circuit.

Abstract: An optical receiver includes a light-receiving element, a bias circuit, an output circuit, and a damping resistor. The light-receiving element converts an optical signal into an electrical signal. The bias circuit applies a DC bias voltage to the light-receiving element. The output circuit outputs, from an output terminal, a voltage corresponding to an optical current generated by the light-receiving element. The damping resistor is connected between the light-receiving element and the output terminal in the output circuit and has a resistance set to serve as a critical damping condition in combination with a junction capacitance and a lead inductance of the light-receiving element.

Abstract: Disclosed is a digital signal regenerator responsive to a data bit stream having a predetermined bit rate for generating a retimed data bit stream. The digital signal regenerator includes a transition detect and pulse generating circuit responsive to the data bit stream for detecting transition positions between two different states of the data bit stream and for generating respective width-variable pulses at the transition positions. Filtering circuitry responsive to the width-variable pulses is provided for extracting a timing wave from the data bit stream. A clock-pulse generating circuit responsive to the timing wave is provided for generating a clock pulse sequence. A discriminating circuit responsive to the clock pulse sequence is lastly provided for discriminating between levels "1" and "0" of the data bit sequence to generate the retimed data bit stream.

Abstract: First and second photoelectric converting circuits are provided to be connected to first and second input terminals of a differential amplifier, respectively. The first and second photoelectric converting circuits are optically coupled to a common optical fiber, so that first and second electric signals which are reverse in polarity are supplied to the first and second input terminals. Consequently, noise superposed, for instance, on a power supply line is supplied through the first and second photoelectric converting circuits to the first and second input terminals of the differential amplifier with the same phase as each other, so that the noises are cancelled in the differential amplifier.

Abstract: An LED driver circuit of a digital optical transmitter for an optical fiber data link includes a differential amplifier with emitter coupled transistors, an LED being connected to the collector of one of the emitter coupled transistors. A current source is connected to the common emitters to enable switching of the emitter coupled transistors in response to an input signal. The input signal, a first delayed input signal and a second delayed input signal, are applied to the current source through an OR circuit, to render the current source conductive in response to said input signal, the first delayed input signal or the second delayed input signal. The first delayed input signal and an inverted first delayed input signal switch the emitter coupled transistors when the current source is conductive. As the current source is conductive at the transistor switching times, high speed switching with smooth charging and discharging of the LED junction capacitance is achieved.