Patents by Inventor Yoshihiro Ueoka

Yoshihiro Ueoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200266304
    Abstract: A laminated body comprising a substrate, one or more layers selected from a contact resistance reducing layer and a reduction suppressing layer, a Schottky electrode layer and a metal oxide semiconductor layer in this order.
    Type: Application
    Filed: December 26, 2016
    Publication date: August 20, 2020
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Yoshihiro UEOKA, Takashi SEKIYA, Shigekazu TOMAI, Emi KAWASHIMA, Yuki TSURUMA, Motohiro TAKESHIMA
  • Patent number: 10620453
    Abstract: In a spectacle lens including a permanent mark arranged on a concave surface, a layout mark indicating a predetermined reference position on a convex surface is arranged on the convex surface.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: April 14, 2020
    Assignee: HOYA LENS THAILAND LTD.
    Inventors: Yoshihiro Kikuchi, Kenta Ueoka
  • Patent number: 10374045
    Abstract: A semiconductor device 1 which comprises a pair of an ohmic electrode 20 and a Schottky electrode 10 separated from each other, and a semiconductor layer 30 in contact with the ohmic electrode 20 and the Schottky electrode 10, and which satisfies the following formula (I): n < ? ? ? V e qL 2 ( I ) in which n is a carrier concentration (cm?3) of the semiconductor layer, ? is a dielectric constant (F/cm) of the semiconductor layer, Ve is a forward effective voltage (V) between the ohmic electrode and the Schottky electrode, q is an elementary charge (C), and L is a distance (cm) between the ohmic electrode and the Schottky electrode.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: August 6, 2019
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Yuki Tsuruma, Takashi Sekiya, Shigekazu Tomai, Emi Kawashima, Yoshihiro Ueoka
  • Publication number: 20190237556
    Abstract: A structure including a metal oxide semiconductor layer and a noble metal oxide layer, wherein the metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other, and a film thickness of the noble metal oxide layer is more than 10 nm.
    Type: Application
    Filed: October 11, 2017
    Publication date: August 1, 2019
    Applicant: Idemitsu Kosan Co., Ltd.
    Inventors: Yuki TSURUMA, Emi KAWASHIMA, Yoshikazu NAGASAKI, Takashi SEKIYA, Yoshihiro UEOKA
  • Patent number: 10340356
    Abstract: A laminated body comprising a substrate, an ohmic electrode layer, a metal oxide semiconductor layer, a Schottky electrode layer and a buffer electrode layer in this order, wherein a reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: July 2, 2019
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Emi Kawashima, Takashi Sekiya, Yuki Tsuruma, Yoshihiro Ueoka, Shigekazu Tomai, Motohiro Takeshima
  • Publication number: 20190013389
    Abstract: A laminated body comprising a substrate, an ohmic electrode layer, a metal oxide semiconductor layer, a Schottky electrode layer and a buffer electrode layer in this order, wherein a reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer.
    Type: Application
    Filed: December 26, 2016
    Publication date: January 10, 2019
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Emi KAWASHIMA, Takashi SEKIYA, Yuki TSURUMA, Yoshihiro UEOKA, Shigekazu TOMAI, Motohiro TAKESHIMA
  • Publication number: 20190006473
    Abstract: A semiconductor device 1 which comprises a pair of an ohmic electrode 20 and a Schottky electrode 10 separated from each other, and a semiconductor layer 30 in contact with the ohmic electrode 20 and the Schottky electrode 10, and which satisfies the following formula (I): n < ? ? ? V e qL 2 ( I ) in which n is a carrier concentration (cm?3) of the semiconductor layer, ? is a dielectric constant (F/cm) of the semiconductor layer, Ve is a forward effective voltage (V) between the ohmic electrode and the Schottky electrode, q is an elementary charge (C), and L is a distance (cm) between the ohmic electrode and the Schottky electrode.
    Type: Application
    Filed: December 21, 2016
    Publication date: January 3, 2019
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Yuki TSURUMA, Takashi SEKIYA, Shigekazu TOMAI, Emi KAWASHIMA, Yoshihiro UEOKA
  • Patent number: 9117740
    Abstract: The invention provides an SiC semiconductor element having fewer interface defects at the interface between the SiC and the insulating film of the SiC semiconductor, as well as improved channel mobility. The semiconductor element is provided with at least an SiC semiconductor substrate and an insulating film in contact with the substrate, wherein the insulating film is formed on a specific crystal plane of the SiC semiconductor substrate, the specific crystal plane being a plane having an off-angle of 10-20° relative to the {11-20} plane toward the [000-1] direction or at an off-angle of 70-80° relative to the (000-1) plane toward the <11-20> direction. Through the use of a specific crystal plane unknown in the prior art, interface defects between the SiC semiconductor substrate and the insulating film can be reduced, and channel mobility of the semiconductor element can be improved.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: August 25, 2015
    Assignee: NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hiroshi Yano, Yoshihiro Ueoka
  • Publication number: 20130285069
    Abstract: The invention provides an SiC semiconductor element having fewer interface defects at the interface between the SiC and the insulating film of the SiC semiconductor, as well as improved channel mobility. The semiconductor element is provided with at least an SiC semiconductor substrate and an insulating film in contact with the substrate, wherein the insulating film is formed on a specific crystal plane of the SiC semiconductor substrate, the specific crystal plane being a plane having an off-angle of 10-20° relative to the {11-20} plane toward the [000-1] direction or at an off-angle of 70-80° relative to the (000-1) plane toward the <11-20> direction. Through the use of a specific crystal plane unknown in the prior art, interface defects between the SiC semiconductor substrate and the insulating film can be reduced, and channel mobility of the semiconductor element can be improved.
    Type: Application
    Filed: August 12, 2011
    Publication date: October 31, 2013
    Applicant: NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hiroshi Yano, Yoshihiro Ueoka