Patents by Inventor Yoshihiro Ueoka
Yoshihiro Ueoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230143194Abstract: Provided are a crack-free laminated film and a structure including this laminated film. This laminated film includes: a buffer layer; and at least one layer of gallium nitride base film disposed on the buffer layer. Moreover, the compression stress of the entire laminated film is ?2.0 to 5.0 GPa.Type: ApplicationFiled: March 29, 2021Publication date: May 11, 2023Inventors: Yuya SUEMOTO, Yoshihiro UEOKA, Masami MESUDA
-
Publication number: 20220393073Abstract: A stacked body may include a support, a buffer layer, and an electrode layer, in this order, wherein the buffer layer may include one or more metals selected from the group consisting of Ga, Al, In, and Zn, and oxygen, the electrode layer comprises an oxide of magnesium and an oxide of zinc, and the electrode layer has a half width of a diffraction peak observed at 2?=34.8±0.5 deg in X-ray diffraction measurement of 0.43 deg or smaller.Type: ApplicationFiled: November 2, 2020Publication date: December 8, 2022Applicants: IDEMITSU KOSAN CO.,LTD., NATIONAL UNIVERSITY CORPORATION TOKAI NATIONAL HIGHER EDUCATION AND RESEARCH SYSTEM, NIKKISO CO., LTD.Inventors: Shigekazu TOMAI, Yoshihiro UEOKA, Satoshi KATSUMATA, Maki KUSHIMOTO, Manato DEKI, Yoshio HONDA, Hiroshi AMANO
-
Publication number: 20220356118Abstract: An oxide sintered body may include zinc, magnesium, a positive trivalent or positive tetravalent metal element X, and oxygen as constituent elements. The atomic ratio of the metal element X to the sum of the zinc, the magnesium, and the metal element X [X/(Zn+Mg+X)] may be 0.0001 or more and 0.6 or less. The atomic ratio of the magnesium to the sum of the zinc and the magnesium [Mg/(Zn+Mg)] may be 0.25 or more and 0.8 or less.Type: ApplicationFiled: June 24, 2020Publication date: November 10, 2022Applicant: IDEMITSU KOSAN CO.,LTD.Inventors: Shigekazu TOMAI, Yoshihiro UEOKA, Satoshi KATSUMATA, Kenichi SASAKI
-
Patent number: 11434172Abstract: A sintered body, containing zinc, magnesium and oxygen as constituent elements, wherein the atomic ratio of zinc to the sum of zinc and magnesium [Zn/(Zn+Mg)] is 0.20 to 0.75, the atomic ratio of magnesium to the sum of zinc and magnesium [Mg/(Zn+Mg)] is 0.25 to 0.80, and the sintered body consists of a single crystal structure as measured by X-ray diffraction.Type: GrantFiled: October 30, 2019Date of Patent: September 6, 2022Assignee: IDEMITSU KOSAN CO., LTD.Inventors: Shigekazu Tomai, Yoshihiro Ueoka, Satoshi Katsumata, Kenichi Sasaki, Masashi Oyama
-
Publication number: 20220037561Abstract: A stacked body comprising: a semiconductor layer comprising a group III-V nitride semiconductor, and an electrode layer, wherein the electrode layer comprises magnesium oxide and zinc oxide, wherein the molar ratio of magnesium based on the sum of magnesium and zinc of the electrode layer [Mg/(Mg+Zn)] is 0.25 or more and 0.75 or less, and conductivity of the electrode layer is 1.0×10?2 S/cm or more.Type: ApplicationFiled: September 26, 2019Publication date: February 3, 2022Applicants: IDEMITSU KOSAN CO.,LTD., NATIONAL UNIVERSITY CORPORATION TOKAI NATIONAL HIGHER EDUCATION AND RESEARCH SYSTEM, NIKKISO CO., LTD.Inventors: Yoshihiro UEOKA, Shigekazu TOMAI, Satoshi KATSUMATA, Maki KUSHIMOTO, Manato DEKI, Yoshio HONDA, Hiroshi AMANO
-
Publication number: 20220002205Abstract: A sintered body, containing zinc, magnesium and oxygen as constituent elements, wherein the atomic ratio of zinc to the sum of zinc and magnesium [Zn/(Zn+Mg)] is 0.20 to 0.75, the atomic ratio of magnesium to the sum of zinc and magnesium [Mg/(Zn+Mg)] is 0.25 to 0.80, and the sintered body consists of a single crystal structure as measured by X-ray diffraction.Type: ApplicationFiled: October 30, 2019Publication date: January 6, 2022Applicant: IDEMITSU KOSAN CO.,LTD.Inventors: Shigekazu TOMAI, Yoshihiro UEOKA, Satoshi KATSUMATA, Kenichi SASAKI, Masashi OYAMA
-
Patent number: 11189737Abstract: A laminated body comprising a substrate, one or more layers selected from a contact resistance reducing layer and a reduction suppressing layer, a Schottky electrode layer and a metal oxide semiconductor layer in this order.Type: GrantFiled: December 26, 2016Date of Patent: November 30, 2021Assignee: IDEMITSU KOSAN CO., LTD.Inventors: Yoshihiro Ueoka, Takashi Sekiya, Shigekazu Tomai, Emi Kawashima, Yuki Tsuruma, Motohiro Takeshima
-
Patent number: 11018238Abstract: A structure including a metal oxide semiconductor layer and a noble metal oxide layer, wherein the metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other, and a film thickness of the noble metal oxide layer is more than 10 nm.Type: GrantFiled: October 11, 2017Date of Patent: May 25, 2021Assignee: IDEMITSU KOSAN CO., LTD.Inventors: Yuki Tsuruma, Emi Kawashima, Yoshikazu Nagasaki, Takashi Sekiya, Yoshihiro Ueoka
-
Publication number: 20200266304Abstract: A laminated body comprising a substrate, one or more layers selected from a contact resistance reducing layer and a reduction suppressing layer, a Schottky electrode layer and a metal oxide semiconductor layer in this order.Type: ApplicationFiled: December 26, 2016Publication date: August 20, 2020Applicant: IDEMITSU KOSAN CO., LTD.Inventors: Yoshihiro UEOKA, Takashi SEKIYA, Shigekazu TOMAI, Emi KAWASHIMA, Yuki TSURUMA, Motohiro TAKESHIMA
-
Patent number: 10374045Abstract: A semiconductor device 1 which comprises a pair of an ohmic electrode 20 and a Schottky electrode 10 separated from each other, and a semiconductor layer 30 in contact with the ohmic electrode 20 and the Schottky electrode 10, and which satisfies the following formula (I): n < ? ? ? V e qL 2 ( I ) in which n is a carrier concentration (cm?3) of the semiconductor layer, ? is a dielectric constant (F/cm) of the semiconductor layer, Ve is a forward effective voltage (V) between the ohmic electrode and the Schottky electrode, q is an elementary charge (C), and L is a distance (cm) between the ohmic electrode and the Schottky electrode.Type: GrantFiled: December 21, 2016Date of Patent: August 6, 2019Assignee: IDEMITSU KOSAN CO., LTD.Inventors: Yuki Tsuruma, Takashi Sekiya, Shigekazu Tomai, Emi Kawashima, Yoshihiro Ueoka
-
Publication number: 20190237556Abstract: A structure including a metal oxide semiconductor layer and a noble metal oxide layer, wherein the metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other, and a film thickness of the noble metal oxide layer is more than 10 nm.Type: ApplicationFiled: October 11, 2017Publication date: August 1, 2019Applicant: Idemitsu Kosan Co., Ltd.Inventors: Yuki TSURUMA, Emi KAWASHIMA, Yoshikazu NAGASAKI, Takashi SEKIYA, Yoshihiro UEOKA
-
Patent number: 10340356Abstract: A laminated body comprising a substrate, an ohmic electrode layer, a metal oxide semiconductor layer, a Schottky electrode layer and a buffer electrode layer in this order, wherein a reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer.Type: GrantFiled: December 26, 2016Date of Patent: July 2, 2019Assignee: IDEMITSU KOSAN CO., LTD.Inventors: Emi Kawashima, Takashi Sekiya, Yuki Tsuruma, Yoshihiro Ueoka, Shigekazu Tomai, Motohiro Takeshima
-
Publication number: 20190013389Abstract: A laminated body comprising a substrate, an ohmic electrode layer, a metal oxide semiconductor layer, a Schottky electrode layer and a buffer electrode layer in this order, wherein a reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer.Type: ApplicationFiled: December 26, 2016Publication date: January 10, 2019Applicant: IDEMITSU KOSAN CO., LTD.Inventors: Emi KAWASHIMA, Takashi SEKIYA, Yuki TSURUMA, Yoshihiro UEOKA, Shigekazu TOMAI, Motohiro TAKESHIMA
-
Publication number: 20190006473Abstract: A semiconductor device 1 which comprises a pair of an ohmic electrode 20 and a Schottky electrode 10 separated from each other, and a semiconductor layer 30 in contact with the ohmic electrode 20 and the Schottky electrode 10, and which satisfies the following formula (I): n < ? ? ? V e qL 2 ( I ) in which n is a carrier concentration (cm?3) of the semiconductor layer, ? is a dielectric constant (F/cm) of the semiconductor layer, Ve is a forward effective voltage (V) between the ohmic electrode and the Schottky electrode, q is an elementary charge (C), and L is a distance (cm) between the ohmic electrode and the Schottky electrode.Type: ApplicationFiled: December 21, 2016Publication date: January 3, 2019Applicant: IDEMITSU KOSAN CO., LTD.Inventors: Yuki TSURUMA, Takashi SEKIYA, Shigekazu TOMAI, Emi KAWASHIMA, Yoshihiro UEOKA
-
Patent number: 9117740Abstract: The invention provides an SiC semiconductor element having fewer interface defects at the interface between the SiC and the insulating film of the SiC semiconductor, as well as improved channel mobility. The semiconductor element is provided with at least an SiC semiconductor substrate and an insulating film in contact with the substrate, wherein the insulating film is formed on a specific crystal plane of the SiC semiconductor substrate, the specific crystal plane being a plane having an off-angle of 10-20° relative to the {11-20} plane toward the [000-1] direction or at an off-angle of 70-80° relative to the (000-1) plane toward the <11-20> direction. Through the use of a specific crystal plane unknown in the prior art, interface defects between the SiC semiconductor substrate and the insulating film can be reduced, and channel mobility of the semiconductor element can be improved.Type: GrantFiled: August 12, 2011Date of Patent: August 25, 2015Assignee: NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Hiroshi Yano, Yoshihiro Ueoka
-
Publication number: 20130285069Abstract: The invention provides an SiC semiconductor element having fewer interface defects at the interface between the SiC and the insulating film of the SiC semiconductor, as well as improved channel mobility. The semiconductor element is provided with at least an SiC semiconductor substrate and an insulating film in contact with the substrate, wherein the insulating film is formed on a specific crystal plane of the SiC semiconductor substrate, the specific crystal plane being a plane having an off-angle of 10-20° relative to the {11-20} plane toward the [000-1] direction or at an off-angle of 70-80° relative to the (000-1) plane toward the <11-20> direction. Through the use of a specific crystal plane unknown in the prior art, interface defects between the SiC semiconductor substrate and the insulating film can be reduced, and channel mobility of the semiconductor element can be improved.Type: ApplicationFiled: August 12, 2011Publication date: October 31, 2013Applicant: NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Hiroshi Yano, Yoshihiro Ueoka