Patents by Inventor Yoshihiro Watanabe

Yoshihiro Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190342997
    Abstract: An electronic device is provided and including a first substrate including a first glass substrate and a first conductive layer; a second substrate including: a second glass substrate which is disposed to be apart from the first conductive layer and includes a first surface opposed to the first conductive layer and a second surface opposite to the first surface, a second conductive layer disposed on the second surface, and a first hole penetrating the second glass substrate; and a connecting material electrically connecting the first conductive layer and the second conductive layer via the first hole, wherein the first hole is shaped as a funnel, and the connecting material includes a hollow part in which an insulative filling material is filled.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 7, 2019
    Inventors: Shuichi OSAWA, Yoshikatsu IMAZEKI, Yoichi KAMIJO, Yoshihiro WATANABE
  • Patent number: 10437372
    Abstract: According to one embodiment, an electronic device includes a first substrate, a second substrate and a connecting material. The first substrate includes a first basement and a first conductive layer. The second substrate includes a second basement having a first hole a second conductive layer having a second hole. The first surface of the second basement opposes the first conductive layer and is spaced therefrom. The second surface opposite to the first surface includes a first flat portion exposed from the second conductive layer. The connecting material is filled into the first hole electrically connect the first conductive layer and the second conductive layer to each other.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 8, 2019
    Assignee: Japan Display Inc.
    Inventors: Yoshihiro Watanabe, Yoshikatsu Imazeki, Yoichi Kamijo, Shuichi Osawa
  • Patent number: 10412832
    Abstract: According to one embodiment, the display device includes a first substrate, a second substrate and a connecting material. The first substrate includes a first basement and a first conductive layer. The second substrate includes a second basement including a first surface, a second surface and a first hole located in the non-display area, and a second conductive layer provided on the second surface. The connecting material electrically connects the first conductive layer and the second conductive layer to each other via the first hole. The connecting material covers at least partially a portion of an opening edge belonging to the second region but does not cover a portion belonging to the first region.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: September 10, 2019
    Assignee: JAPAN DISPLAY INC.
    Inventors: Yoshikatsu Imazeki, Yoichi Kamijo, Shuichi Osawa, Yoshihiro Watanabe
  • Patent number: 10401696
    Abstract: According to one embodiment, an electronic apparatus includes a first substrate, a second substrate, and a connecting material. The second substrate includes a second basement and a second conductive layer. The second basement has a third surface opposed to the first conductive layer and a fourth surface and is spaced apart from the first conductive layer. The second substrate has a first hole penetrating the second basement. The first substrate has a second hole. A third opening of the second hole is smaller than a first opening of the first hole. A connecting material connects the first conductive layer and the second conductive layer via the first hole.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: September 3, 2019
    Assignee: Japan Display Inc.
    Inventors: Yoshihiro Watanabe, Yoshikatsu Imazeki, Yoichi Kamijo, Shuichi Osawa
  • Patent number: 10405428
    Abstract: According to one embodiment, an electronic device includes a first substrate including a first basement and a first conductive layer, a second substrate including a second basement which is disposed to be apart from the first conductive layer and includes a first surface opposed to the first conductive layer and a second surface opposite to the first surface, and a second conductive layer disposed on the second surface, the second substrate including a first hole passing through the second basement, and a connecting material passing through the first hole to electrically connect the first conductive layer and the second conductive layer, wherein the first hole is shaped as a funnel.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: September 3, 2019
    Assignee: Japan Display Inc.
    Inventors: Shuichi Osawa, Yoshikatsu Imazeki, Yoichi Kamijo, Yoshihiro Watanabe
  • Patent number: 10381565
    Abstract: According to one embodiment, a display device includes first to third substrates, a display function layer and a first connecting structure. The first substrate includes a first basement and a first conductive layer. The second substrate includes a second basement. The third substrate includes a third basement. The first connecting structure includes a first contact hole which penetrates at least the second basement and a first connecting material which electrically connects the first conductive layer and the second conductive layer to each other via the first contact hole, and electrically connects the first conductive layer and the second conductive layer to each other.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: August 13, 2019
    Assignee: Japan Display Inc.
    Inventors: Yoichi Kamijo, Shuichi Osawa, Yoshihiro Watanabe, Yoshikatsu Imazeki
  • Patent number: 10363748
    Abstract: A liquid ejecting apparatus includes a liquid ejecting head that ejects a liquid, and a liquid storage section that stores the liquid to be fed to the liquid ejecting head. The liquid storage section includes a storage tank of which at least part is provided with a flexible section having flexibility, a liquid feed port to feed the liquid to the liquid ejecting head, and a liquid filling inlet to refill the liquid. The liquid filling inlet is capable of opening and closing and capable of being sealed. Moreover, the storage tank has a volume that can be changed by the flexible section deforming.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: July 30, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Yoshihiro Watanabe
  • Publication number: 20190228497
    Abstract: To perform inter-pixel image processing with lower latency and higher speed. An image sensor includes: a pixel array unit in which pixels having a photoelectric conversion function are arranged in an array; an AD conversion unit configured to perform AD conversion processing on pixel signals output from the pixels in parallel for each column of the pixels of the pixel array unit; a memory unit configured to hold pixel signals of any number of rows subjected to AD conversion in the AD conversion unit for each column of the pixels; an inter-pixel image processing unit configured to read pixel signals of any rows and columns from the memory unit, and perform computing between the pixel signals in parallel for each column of the pixels; and an output circuit configured to control output, to an outside, of pixel signals output from the AD conversion unit and pixel signals output from the inter-pixel image processing unit. The present technology can be applied to, for example, a CMOS image sensor.
    Type: Application
    Filed: August 23, 2017
    Publication date: July 25, 2019
    Applicants: SONY CORPORATION, THE UNIVERSITY OF TOKYO
    Inventors: Yoshinori MURAMATSU, Shuji UEHARA, Hironobu KATAYAMA, Tomohiro YAMAZAKI, Masatoshi ISHIKAWA, Yoshihiro WATANABE
  • Publication number: 20190204976
    Abstract: According to one embodiment, an electronic device includes a first substrate, a second substrate and a connecting material. The first substrate includes a first basement and a first conductive layer. The second substrate includes a second basement having a first hole a second conductive layer having a second hole. The first surface of the second basement opposes the first conductive layer and is spaced therefrom. The second surface opposite to the first surface includes a first flat portion exposed from the second conductive layer. The connecting material is filled into the first hole electrically connect the first conductive layer and the second conductive layer to each other.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 4, 2019
    Inventors: Yoshihiro WATANABE, Yoshikatsu IMAZEKI, Yoichi KAMIJO, Shuichi OSAWA
  • Publication number: 20190206022
    Abstract: [Object] To reduce a scale of an arithmetic processing unit which performs an arithmetic process between frames in a sensor. [Solution] A frame memory stores pixel data of a frame that transitions in time sequence. An inter-frame arithmetic processing unit implements a predetermined arithmetic by column parallel in a row unit on the pixel data of a current frame and the pixel data of a past frame stored in the frame memory and updates the pixel data of the past frame stored in the frame memory on the basis of a result of the predetermined arithmetic.
    Type: Application
    Filed: August 23, 2017
    Publication date: July 4, 2019
    Inventors: Hironobu KATAYAMA, Shuji UEHARA, Yoshinori MURAMATSU, Tomohiro YAMAZAKI, Yoshihiro WATANABE, Masatoshi ISHIKAWA
  • Patent number: 10333467
    Abstract: A crystal oscillator includes a surface mount type crystal unit and a mounting substrate. The surface mount type crystal unit includes a ceramic container. The surface mount type crystal unit has a rectangular shape as a planar shape. The mounting substrate includes a ceramic substrate on which an electronic component is mounted, the mounting substrate having a rectangular shape as a planar shape. The crystal oscillator has a structure where the surface mount type crystal unit and the mounting substrate are laminated, and both terminals of the surface mount type crystal unit and the mounting substrate are connected with a bonding material. The mounting substrate and the surface mount type crystal unit are connected in a positional relationship where a long side of the mounting substrate and a long side of the surface mount type crystal unit are orthogonal.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: June 25, 2019
    Assignee: NIHON DEMPA KOGYO CO., LTD.
    Inventor: Yoshihiro Watanabe
  • Publication number: 20190179465
    Abstract: According to one embodiment, a display device includes a display panel including a display area and a non-display area including a first area and a second area. The display panel includes a first substrate, a second substrate including a contact hole crossing a borderline, a protection layer provided over the display area and the first area, and a connecting material. An outer edge of the protection layer includes one first outer edge located on the borderline, another first outer edge located on the borderline opposed to the one first outer edge across the contact hole, and a second outer edge provided in the first area, connected to an end of the one first outer edge and extending along the contact hole.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 13, 2019
    Inventors: Koichi MIYASAKA, Yoshikatsu Imazeki, Yoichi Kamijo, Shuichi Osawa, Yoshihiro Watanabe
  • Publication number: 20190171056
    Abstract: According to one embodiment, a display device includes a first substrate including a first basement and a first conductive layer, a second substrate including a second basement and a second conductive layer, and a display function layer. A second end surface of the second basement includes a flat portion located in a same plane as a first end surface of the first basement, and a first concave portion formed toward an inside of the second basement with respect to the flat portion. A connecting material which electrically connects the first conductive layer and the second conductive layer is provided in the first concave portion.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 6, 2019
    Inventors: Shuichi OSAWA, Yoshikatsu IMAZEKI, Yoichi KAMIJO, Yoshihiro WATANABE
  • Patent number: 10310692
    Abstract: According to one embodiment, a display device includes an organic insulating layer located between an first basement and an second basement, a first hole penetrating the second basement and the organic insulating layer, a connecting material provided via the first hole to electrically connects a first terminal and a second terminal to each other and a filling member covering the connecting material and filled in the first hole, and the protective member includes an exposure area in which the filling member is disposed, and a thickness from the second basement to an upper surface of the filling member is substantially equal to a thickness from the second basement to an upper surface of the protective member.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 4, 2019
    Assignee: Japan Display Inc.
    Inventors: Yoichi Kamijo, Yoshikatsu Imazeki, Shuichi Osawa, Yoshihiro Watanabe
  • Publication number: 20190148668
    Abstract: According to one embodiment, a display device includes a display panel including a first surface over a display portion and a non-display portion therearound, a cover including a second surface opposing the first surface and an adhesive layer in contact with the first surface and the second surface, and the first surface includes a convexity projecting toward the cover in the non-display portion, and the second surface includes a concavity overlapping the convexity.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 16, 2019
    Inventors: Yoichi KAMIJO, Yoshikatsu IMAZEKI, Shuichi OSAWA, Yoshihiro WATANABE, Koichi MIYASAKA
  • Publication number: 20190138134
    Abstract: To reduce disturbances in display of images due to static electricity without deteriorating optical properties in a display. The display includes a conductive pattern provided on the upper surface of the substrate, a protection layer provided on the upper surface of the substrate to cover the conductive pattern, and a conductive layer provided on the protection layer. The sheet resistance of the conductive pattern is not more than 8 ?/square. A ratio of the total sum of areas of portions of the plurality of sub-pixels that overlap the conductive pattern in a plan view to the total sum of the areas of the plurality of sub-pixels is 1 to 22%. A sheet resistance of the conductive layer is higher than the sheet resistance of the conductive pattern.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Inventors: Masanobu Ikeda, Koji Ishizaki, Hayato Kurasawa, Yoshihiro Watanabe, Toshimasa Ishigaki, Daisuke Sonoda, Tatsuya Ide
  • Patent number: 10268299
    Abstract: According to one embodiment, an electronic device includes a first substrate, a second substrate and a connecting material. The first substrate includes a first basement and a first conductive layer. The second substrate includes a second basement having a first hole a second conductive layer having a second hole. The first surface of the second basement opposes the first conductive layer and is spaced therefrom. The second surface opposite to the first surface includes a first flat portion exposed from the second conductive layer. The connecting material is filled into the first hole electrically connect the first conductive layer and the second conductive layer to each other.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: April 23, 2019
    Assignee: Japan Display Inc.
    Inventors: Yoshihiro Watanabe, Yoshikatsu Imazeki, Yoichi Kamijo, Shuichi Osawa
  • Publication number: 20190066608
    Abstract: According to one embodiment, an electronic device includes a display panel having a plurality of pixels arranged in a matrix. Gray levels of the pixels are determined according to a gray level of a first frame, a gray level of a second frame and positions of the pixels in the matrix.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 28, 2019
    Applicant: Japan Display Inc.
    Inventor: Yoshihiro WATANABE
  • Patent number: 10216345
    Abstract: To reduce disturbances in display of images due to static electricity without deteriorating optical properties in a display. The display includes a conductive pattern provided on the upper surface of the substrate, a protection layer provided on the upper surface of the substrate to cover the conductive pattern, and a conductive layer provided on the protection layer. The sheet resistance of the conductive pattern is not more than 8 ?/square. A ratio of the total sum of areas of portions of the plurality of sub-pixels that overlap the conductive pattern in a plan view to the total sum of the areas of the plurality of sub-pixels is 1 to 22%. A sheet resistance of the conductive layer is higher than the sheet resistance of the conductive pattern.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: February 26, 2019
    Assignee: Japan Display Inc.
    Inventors: Masanobu Ikeda, Koji Ishizaki, Hayato Kurasawa, Yoshihiro Watanabe, Toshimasa Ishigaki, Daisuke Sonoda, Tatsuya Ide
  • Publication number: 20190033641
    Abstract: A display apparatus includes a first substrate, a second substrate facing the first substrate, lead wirings provided on the first substrate or the second substrate and a first insulator part provided on an upper surface of the second substrate. The lead wirings are arranged in a peripheral region when seen in a plan view and the first insulator part is arranged so as to overlap a display region when seen in a plan view. Second insulator parts or spaces with a permittivity lower than a permittivity of the first insulator part are provided at sides of the first insulator part. The second insulator parts or the spaces are arranged so as to overlap the lead wirings in the peripheral region when seen in a plan view.
    Type: Application
    Filed: October 3, 2018
    Publication date: January 31, 2019
    Inventors: Koji Ishizaki, Masanobu Ikeda, Hayato Kurasawa, Yoshihiro Watanabe