Patents by Inventor Yoshihiro Yanai
Yoshihiro Yanai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11037948Abstract: A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells; and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region.Type: GrantFiled: September 5, 2019Date of Patent: June 15, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Sonoe Matsushita, Takahito Nishimura, Kazuyuki Yoshimochi, Yoshihiro Yanai, Satoshi Usui
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Patent number: 10991712Abstract: An end of a stacked-structure of conductive and insulating layers above a substrate has a staircase structure. The staircase includes a step pair. The risers of steps are opposed to each other. The step pairs are provided at different levels in the form in the staircase. First contact-plugs are provided on treads of respective steps of the first step part. A second contact-plug is provided in either an intermediate region between the first and the second steps of the step pair or the second step to extend in the stacked structure in a direction in which the conductive and insulating layers are stacked. A CMOS circuit is provided below the stacked structure and is connected to the second contact-plug. The second contact-plug is provided in either the intermediate region on which the first contact-plug is not formed or the second step on which the first contact-plug is not formed.Type: GrantFiled: February 11, 2019Date of Patent: April 27, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yoshihiro Yanai
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Publication number: 20200295022Abstract: A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells; and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region.Type: ApplicationFiled: September 5, 2019Publication date: September 17, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Sonoe Matsushita, Takahito Nishimura, Kazuyuki Yoshimochi, Yoshihiro Yanai, Satoshi Usui
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Publication number: 20190348430Abstract: An end of a stacked-structure of conductive and insulating layers above a substrate has a staircase structure. The staircase includes a step pair. The risers of steps are opposed to each other. The step pairs are provided at different levels in the form in the staircase. First contact-plugs are provided on treads of respective steps of the first step part. A second contact-plug is provided in either an intermediate region between the first and the second steps of the step pair or the second step to extend in the stacked structure in a direction in which the conductive and insulating layers are stacked. A CMOS circuit is provided below the stacked structure and is connected to the second contact-plug. The second contact-plug is provided in either the intermediate region on which the first contact-plug is not formed or the second step on which the first contact-plug is not formed.Type: ApplicationFiled: February 11, 2019Publication date: November 14, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Yoshihiro YANAI
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Patent number: 10176290Abstract: According to one embodiment, stepped structure is formed on a semiconductor substrate, a processing film is formed to cover the stepped structure, a resist film is formed on the processing film in such a manner as to be thinner at a higher portion of the stepped structure than at a lower portion of the same, and the resist film and the processing film are etched to flatten the processing film.Type: GrantFiled: December 19, 2016Date of Patent: January 8, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takuro Urayama, Yoshihiro Yanai, Seiro Miyoshi
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Patent number: 10153296Abstract: A memory device includes a substrate and a stacked body arranged along a first direction. The stacked body includes electrode films. A configuration of an end portion in a second direction of the stacked body is a staircase configuration. Steps corresponding to the electrode films are formed in the staircase configuration. A first distance between a first step and an end edge of the stacked body in the second direction is shorter than a second distance between a second step and the end edge in the second direction. The first step is positioned at an end portion in a third direction of the stacked body. The second step is positioned at a central portion in the third direction of the stacked body. The first and second steps correspond to two of the electrode films positioned at the same level when counting along the first direction from the substrate side.Type: GrantFiled: July 14, 2017Date of Patent: December 11, 2018Assignee: Toshiba Memory CorporationInventors: Naoyuki Iida, Hideki Inokuma, Naoki Yamamoto, Yoshihiro Yanai
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Patent number: 10120275Abstract: According to one embodiment, a layout region of a mask pattern is divided into N (N is an integer of 2 or larger) units, a main pattern resolved by exposure light is arranged and sub patterns not resolved by the exposure light are arranged outside the main pattern such that distributions of attenuation amount of the exposure light in the divided layout regions are different.Type: GrantFiled: September 2, 2016Date of Patent: November 6, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masakazu Hamasaki, Yoshihiro Yanai, Michiya Takimoto, Naoki Sato, Satoshi Usui, Takaki Hashimoto
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Publication number: 20180247955Abstract: A memory device includes a substrate and a stacked body arranged along a first direction. The stacked body includes electrode films. A configuration of an end portion in a second direction of the stacked body is a staircase configuration. Steps corresponding to the electrode films are formed in the staircase configuration. A first distance between a first step and an end edge of the stacked body in the second direction is shorter than a second distance between a second step and the end edge in the second direction. The first step is positioned at an end portion in a third direction of the stacked body. The second step is positioned at a central portion in the third direction of the stacked body. The first and second steps correspond to two of the electrode films positioned at the same level when counting along the first direction from the substrate side.Type: ApplicationFiled: July 14, 2017Publication date: August 30, 2018Applicant: Toshiba Memory CorporationInventors: Naoyuki IIDA, Hideki INOKUMA, Naoki YAMAMOTO, Yoshihiro YANAI
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Publication number: 20170329887Abstract: According to one embodiment, a layout region of a mask pattern is divided into N (N is an integer of 2 or larger) units, a main pattern resolved by exposure light is arranged and sub patterns not resolved by the exposure light are arranged outside the main pattern such that distributions of attenuation amount of the exposure light in the divided layout regions are different.Type: ApplicationFiled: September 2, 2016Publication date: November 16, 2017Applicant: TOSHIBA MEMORY CORPORATIONInventors: Masakazu HAMASAKI, Yoshihiro Yanai, Michiya Takimoto, Naoki Sato, Satoshi Usui, Takaki Hashimoto
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Publication number: 20170098029Abstract: According to one embodiment, stepped structure is formed on a semiconductor substrate, a processing film is formed to cover the stepped structure, a resist film is formed on the processing film in such a manner as to be thinner at a higher portion of the stepped structure than at a lower portion of the same, and the resist film and the processing film are etched to flatten the processing film.Type: ApplicationFiled: December 19, 2016Publication date: April 6, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takuro URAYAMA, Yoshihiro YANAI, Seiro MIYOSHI
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Patent number: 9613976Abstract: In general, according to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a memory film, a partitioning member, a first interlayer insulating film, and a first plug. The stacked body is provided on the substrate, and including a plurality of electrode films and a plurality of insulating films. The semiconductor pillar is provided in the stacked body. The partitioning member is provided in the stacked body. The first plug is connected to the semiconductor pillar. A central axis of the first plug is shifted from a central axis of the semiconductor pillar so as to approach the nearest partitioning member.Type: GrantFiled: March 13, 2015Date of Patent: April 4, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiro Shimojo, Masaru Kito, Yoshihiro Yanai
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Publication number: 20170018438Abstract: In a pattern forming method according to an embodiment, a work film to be processed is formed on a substrate, and a resist pattern is formed on the top of the work film. Then, the resist pattern is baked in the bake condition set at positions of the substrate. This forms first inclined surfaces those are not parallel to the top and side surfaces of the work film on the resist pattern. The first inclined surfaces are formed into shapes in accordance with the bake condition at positions of the substrate. Furthermore, the work film is etched using the resist pattern as a mask so as to form a second inclined surface on the work film.Type: ApplicationFiled: September 4, 2015Publication date: January 19, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Yoshihiro YANAI
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Patent number: 9548315Abstract: A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped structure in which an end of a lower first layer is further from the memory cell region than is an end of an upper first layer; and a second stepped structure disposed on the first stepped structure, in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.Type: GrantFiled: September 10, 2015Date of Patent: January 17, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Megumi Ishiduki, Murato Kawai, Tadashi Iguchi, Yoshihiro Yanai, Takuya Inatsuka, Yoichi Minemura, Takuya Mizutani
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Patent number: 9547743Abstract: According to one embodiment, stepped structure is formed on a semiconductor substrate, a processing film is formed to cover the stepped structure, a resist film is formed on the processing film in such a manner as to be thinner at a higher portion of the stepped structure than at a lower portion of the same, and the resist film and the processing film are etched to flatten the processing film.Type: GrantFiled: June 5, 2015Date of Patent: January 17, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Takuro Urayama, Yoshihiro Yanai, Seiro Miyoshi
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Publication number: 20160315094Abstract: A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped structure in which an end of a lower first layer is further from the memory cell region than is an end of an upper first layer; and a second stepped structure disposed on the first stepped structure, in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.Type: ApplicationFiled: September 10, 2015Publication date: October 27, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Megumi ISHIDUKI, Murato KAWAI, Tadashi IGUCHI, Yoshihiro YANAI, Takuya INATSUKA, Yoichi MINEMURA, Takuya MIZUTANI
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Publication number: 20160247679Abstract: According to one embodiment, stepped structure is formed on a semiconductor substrate, a processing film is formed to cover the stepped structure, a resist film is formed on the processing film in such a manner as to be thinner at a higher portion of the stepped structure than at a lower portion of the same, and the resist film and the processing film are etched to flatten the processing film.Type: ApplicationFiled: June 5, 2015Publication date: August 25, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Takuro URAYAMA, Yoshihiro Yanai, Seiro Miyoshi
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Publication number: 20160071866Abstract: According to one embodiment, the first columnar part includes a first channel body and a first charge storage film. The second columnar part includes a second channel body and a second charge storage film. The second columnar part is provided adjacent in the first direction to the first columnar part. The connection part connects a lower end of the first channel body and a lower end of the second channel body. Each of the source layers is connected to an upper end of the first columnar part. Each of the bit lines is connected to an upper end of the second columnar part of every (n+1)-th memory string of a plurality of memory strings arranged in the first direction.Type: ApplicationFiled: August 5, 2015Publication date: March 10, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiro SHIMOJO, Masaru KIDOH, Masaru KITO, Ryota KATSUMATA, Yoshihiro YANAI
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Publication number: 20160071875Abstract: In general, according to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a memory film, a partitioning member, a first interlayer insulating film, and a first plug. The stacked body is provided on the substrate, and including a plurality of electrode films and a plurality of insulating films. The semiconductor pillar is provided in the stacked body. The partitioning member is provided in the stacked body. The first plug is connected to the semiconductor pillar. A central axis of the first plug is shifted from a central axis of the semiconductor pillar so as to approach the nearest partitioning member.Type: ApplicationFiled: March 13, 2015Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiro SHIMOJO, Masaru KITO, Yoshihiro YANAI
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Publication number: 20160071865Abstract: According to one embodiment, the memory strings are disposed in a first direction and a second direction. The source layers extend in the second direction on the memory strings and are separated in the first direction. The bit lines extend in the first direction on the memory strings and are separated in the second direction. The memory string includes a first columnar section, a second columnar section, and a connecting section. The stacked body includes a plurality of blocks separated from one another in the first direction. The source layer is connected to an upper end of the first columnar section. The bit line is connected to an upper end of the second columnar section of the memory string belonging to a block selected out of the plurality of blocks.Type: ApplicationFiled: August 4, 2015Publication date: March 10, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yoshihiro YANAI, Yoshiro Shimojo, Masaru Kito, Masaru Kidoh
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Patent number: 9159726Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate and a memory array. The semiconductor substrate has a first face. The memory array region is provided on the first face and includes a plurality of semiconductor pillars. The semiconductor pillars extend in a first direction perpendicular to the first face. Each of the semiconductor pillars includes a plurality of memory cells connected in series. Each of the semiconductor pillars is disposed at the nodes of a honeycomb shape when viewed in the first direction. When the semiconductor pillars are projected onto a first plane along the first and second directions perpendicular to the first direction, a component in the second direction of an interval between the semiconductor pillars has first and second intervals repeated alternately. The second interval is an integer multiple of the first interval greater than or equal to 2.Type: GrantFiled: March 10, 2014Date of Patent: October 13, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Yamane, Yoshihiro Yanai, Hiromitsu Mashita