Patents by Inventor Yoshihiro Yoshii

Yoshihiro Yoshii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160342512
    Abstract: The invention provides a technique for improving processing performance of I/O commands in a storage system in which ownership of each LU is introduced. The storage system includes: a disk device having storage regions that are managed as a plurality of logical units; a plurality of processors that process read commands to the disk device; and a cache that the processors can use to process the read commands. An owner processor that is in charge of processing to each logical unit is allocated to each logical unit. When decision is made that dirty data is not present in the cache in a target region of the read command, there are a case where the owner processor of a logical unit that includes the target region processes the read command, and a case where a non-owner processor, as the processor other than the owner processor, processes the read command.
    Type: Application
    Filed: January 21, 2014
    Publication date: November 24, 2016
    Inventors: Yuki SAKASHITA, Shintaro KUDO, Yoshihiro YOSHII, Yusuke NONAKA
  • Publication number: 20150350301
    Abstract: The transfer data amount between a server and storage is effectively reduced, and the broadband of an effective band between the server and the storage is realized. An interface device is located in a server module, and, when receiving a read request issued by a server processor, transmits a read command based on the read request to a storage processor. In a case where a reverse-conversion instruction to cause the interface device to perform reverse conversion of post-conversion object data acquired by converting object data of the read request is received from the storage processor, DMA to transfer post-conversion object data stored in the transfer source address on a storage memory to the transfer destination address on the server memory while reverse-converting the post-conversion object data is performed.
    Type: Application
    Filed: July 30, 2015
    Publication date: December 3, 2015
    Inventors: Nobuhiro YOKOI, Mutsumi HOSOYA, Nagamasa MIZUSHIMA, Yoshihiro YOSHII, Masabumi SHIBATA
  • Publication number: 20150339058
    Abstract: A storage controller stores a data block related to a received write command in a first cache memory as an undefined state, and transmits, to a storage device, an undefining write command of requesting to store the data block as an undefined state, the undefining write command being a command associated with an address of a target logical area corresponding to a write destination according to the write command. The storage device has a non-volatile memory configured by a plurality of physical areas, stores a data block related to the undefining write command transmitted from the storage controller in an empty physical area of the plurality of physical areas, and assigns the physical area to the target logical area as a physical area in an undefined state.
    Type: Application
    Filed: March 26, 2013
    Publication date: November 26, 2015
    Inventors: Yoshihiro YOSHII, Sadahiro SUGIMOTO
  • Patent number: 9116858
    Abstract: The transfer data amount between a server and storage is effectively reduced, and the broadband of an effective band between the server and the storage is realized. An interface device is located in a server module, and, when receiving a read request issued by a server processor, transmits a read command based on the read request to a storage processor. In a case where a reverse-conversion instruction to cause the interface device to perform reverse conversion of post-conversion object data acquired by converting object data of the read request is received from the storage processor, DMA to transfer post-conversion object data stored in the transfer source address on a storage memory to the transfer destination address on the server memory while reverse-converting the post-conversion object data is performed.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: August 25, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Nobuhiro Yokoi, Mutsumi Hosoya, Nagamasa Mizushima, Yoshihiro Yoshii, Masabumi Shibata
  • Patent number: 8370578
    Abstract: Provided is a storage controller and method of controlling same which, if part of a storage area of a local memory is used as cache memory, enable an access conflict for access to a parallel bus connected to the local memory to be avoided. A storage controller which exercises control of data between a host system and a storage apparatus, comprising a data transfer control unit which exercises control to transfer the data on the basis of a read/write request from the host system; a cache memory which is connected to the data transfer control unit via a parallel bus; a control unit which is connected to the data transfer control unit via a serial bus; and a local memory which is connected to the control unit via a parallel bus, wherein the control unit decides to assign, from a cache segment of either the cache memory or the local memory, a storage area which stores the data on the basis of a CPU operating rate and a path utilization of the parallel bus connected to the cache memory.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: February 5, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Yoshii, Mitsuru Inoue, Kentaro Shimada, Sadahiro Sugimoto
  • Patent number: 8341348
    Abstract: A computer system having a plurality of controllers for data input/output control is provided, wherein even if a control authority of a processor is transferred to another processor and the computer system migrates control information necessary for a controller to execute data input/output processing, from a shared memory to a local memory for the relevant controller, the computer system prevents the occurrence of unbalanced allocation of a control function necessary for data input/output control between the plurality of controllers; and a load equalization method for such a computer system is also provided.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: December 25, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Yoshii, Shintaro Kudo, Kazuyoshi Serizawa, Masayuki Yamamoto, Sadahiro Sugimoto
  • Publication number: 20120226861
    Abstract: Provided is a storage controller and method of controlling same which, if part of a storage area of a local memory is used as cache memory, enable an access conflict for access to a parallel bus connected to the local memory to be avoided. A storage controller which exercises control of data between a host system and a storage apparatus, comprising a data transfer control unit which exercises control to transfer the data on the basis of a read/write request from the host system; a cache memory which is connected to the data transfer control unit via a parallel bus; a control unit which is connected to the data transfer control unit via a serial bus; and a local memory which is connected to the control unit via a parallel bus, wherein the control unit decides to assign, from a cache segment of either the cache memory or the local memory, a storage area which stores the data on the basis of a CPU operating rate and a path utilization of the parallel bus connected to the cache memory.
    Type: Application
    Filed: March 3, 2011
    Publication date: September 6, 2012
    Inventors: Yoshihiro Yoshii, Mitsuru Inoue, Kentaro Shimada, Sadahiro Sugimoto
  • Publication number: 20110191547
    Abstract: A computer system having a plurality of controllers for data input/output control is provided, wherein even if a control authority of a processor is transferred to another processor and the computer system migrates control information necessary for a controller to execute data input/output processing, from a shared memory to a local memory for the relevant controller, the computer system prevents the occurrence of unbalanced allocation of a control function necessary for data input/output control between the plurality of controllers; and a load equalization method for such a computer system is also provided.
    Type: Application
    Filed: November 19, 2009
    Publication date: August 4, 2011
    Applicant: HITACHI, LTD.
    Inventors: Yoshihiro Yoshii, Shintaro Kudo, Kazuyoshi Serizawa, Masayuki Yamamoto, Sadahiro Sugimoto
  • Publication number: 20030105809
    Abstract: A content delivery method which distributes content from a server to a plurality of customers according to their desired delivery schedules. The server receives delivery schedule information from each user terminal which specifies a desired delivery time. The server then stores the received delivery schedule information into its local storage device. Comparing the present time with each desired delivery time stored in the storage device, the server determines whether any scheduled delivery time is reached. The server delivers specified content to every requesting user terminal when their desired delivery time is reached.
    Type: Application
    Filed: March 26, 2002
    Publication date: June 5, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Yoshihiro Yoshii, Yasuhiko Hongo, Takahiro Endo, Masami Sato
  • Publication number: 20020087675
    Abstract: A resource-utilization-information management unit manages shared-resource information about both available network resources and available media-distribution-system resources. A shared-resource management unit distributes or redistributes the shared resources based on a resource-utilization request from each content distributor. A distribution management unit performs both the reservation management and distribution management of media distribution for each content server within the scope of a resource-utilization right distributed or re-distributed by the shared-resource management unit.
    Type: Application
    Filed: August 24, 2001
    Publication date: July 4, 2002
    Applicant: Fujitsu Limited
    Inventors: Yoshihiro Yoshii, Yasuhiko Hongo, Susumu Miyao, Takahiro Endo